Method and system for ensuring the assertion order of signals in a chip independent of physical layout
View Patent ↗Certain embodiments for ensuring the assertion order of signals in a chip independent of physical layout may comprise receiving a first signal by a first logic block of a plurality of logic blocks integrated within a chip, where the first signal may initiate a reset of a first function within the first logic block. A second signal may be communicated from within the first logic block to a second function within a second logic block of the plurality of logic blocks, and the second signal may be adapted to initiate the second function. The first signal may be the same as a second signal. The reset of the first function may initialize the first function to a known state before the second function may generate an output that may be received by the first function. The first function may place the chip in a test mode when indicated by the generated output of the second function.
1. A method for ensuring the assertion order of signals in a chip, comprising:
receiving a first signal by a first logic block of a plurality of logic blocks integrated within the chip;
communicating a second signal to a second logic block of said plurality of logic blocks, said second logic block performing a second function, wherein said second signal is a buffered version of said first signal that is generated from within said first logic block, said buffered version of said first signal is used to initiate a reset of a first function; and
initiating said second function via said second signal, wherein said reset of said first function initializes said first function to a known state prior to said second function generating an output which is to be received by said first function.
2. The method according to claim 1 , further comprising initiating a test mode of the chip by said first function after said first function receives said generated output of said second function.
3. The method according to claim 1 , further comprising communicating a buffered version of said second signal to an input of a latching device, wherein said latching device is in said second logic block.
4. The method according to claim 3 , further comprising latching a data input to said data latching device utilizing said buffered version of said second signal.
5. The method according to claim 1 , further comprising communicating said first signal to at least a portion of said plurality of logic blocks in a daisy-chained configuration.
6. The method according to claim 1 , further comprising communicating said first signal to at least one output of the chip, wherein said first signal is utilized by at least one off-chip device.
7. The method according to claim 1 , further comprising buffering at least a portion of said second signal within said second logic block.
8. The method according to claim 1 , further comprising receiving said first signal at said first logic block utilizing synchronous logic.
9. The method according to claim 1 , further comprising receiving said second signal at said second logic block utilizing synchronous logic.
10. A system for ensuring the assertion order of signals in a chip, comprising:
a first logic block of a plurality of logic blocks integrated within the chip that receives a first signal;
a second logic block of said plurality of logic blocks that performs a second function and that receives a second signal which initiates said second function, wherein said second signal is a buffered version of said first signal that is generated from within said first logic block wherein said buffered version of said first signal is used to initiate a reset of a first function; and
wherein said reset of said first function initializes said first function to a known state prior to said second function generating an output which is to be received by said first logic block.
11. The system according to claim 10 , wherein said first function commences initiation of a test mode of the chip after said first function receives said generated output.
12. The system according to claim 10 , further comprising a latching device in said second logic block, wherein a buffered version of said second signal is communicated to an input of said latching device.
13. The system according to claim 12 , further comprising a data input to said latching device, wherein said buffered version of said second signal latches said data input to said latching device.
14. The system according to claim 10 , wherein said first signal is communicated to at least a portion of said plurality of logic blocks in a daisy-chained manner.
15. The system according to claim 10 , further comprising at least one output on the chip which communicates said first signal to at least one off-chip device.
16. The system according to claim 10 , further comprising circuitry that buffers at least a portion of said second signal within said second logic block.
17. The system according to claim 10 , further comprising synchronous logic that receives said first signal at said first logic block.
18. The system according to claim 10 , further comprising synchronous logic that receives said second signal at said second logic block.