Thin film transistor array panel
View Patent ↗A thin film transistor array panel is provided, which includes: a substrate; a gate line formed on the substrate; first and second storage electrodes formed on the substrate and disposed opposite each other with respect to the gate line; a gate insulating layer formed in the gate line and the first and the second storage electrodes; a curved data line formed on the gate insulating layer; a thin film transistor connected to the gate line and the data line; a passivation layer formed on the data line and the thin film transistor; a pixel electrode formed on the passivation layer, connected to the thin film transistor, and having an obtuse corner and an acute corner; and an overpass cross over the gate line and connected to the first and the second storage electrodes.
1. A thin film transistor array panel, comprising:
a substrate;
a gate line formed on the substrate;
first and second storage electrodes formed on the substrate and disposed opposite each other with respect to the gate line;
a gate insulating layer formed in the gate line and the first and the second storage electrodes;
a curved data line formed on the gate insulating layer;
a thin film transistor connected to the gate line and the data line;
a passivation layer formed on the data line and the thin film transistor;
a pixel electrode formed on the passivation layer, connected to the thin film transistor, and having an acute corner and an obtuse corner; and
an overpass crossing over the gate line and connected to the first and the second storage electrodes.
2. The thin film transistor array panel of claim 1 , wherein the pixel electrode comprises the same layer as the overpass.
3. The thin film transistor array panel of claim 2 , wherein the overpass is disposed near the acute corner and the acute corner of the pixel electrode is chamfered.
4. The thin film transistor array panel of claim 3 , wherein the pixel electrode has a first major edge and a second major edge shorter than the first major edge and the first and the second major edges approach near the acute corner.
5. The thin film transistor array panel of claim 4 , wherein the acute corner of the pixel electrode includes a first minor edge perpendicular to the first major edge and a second minor edge oblique to the first major edge.
6. The thin film transistor array panel of claim 5 , wherein the first minor edge is shorter than the second minor edge.
7. The thin film transistor array panel of claim 6 , wherein the first minor edge and the second minor edge are connected to each other to make a concave vertex.
8. The thin film transistor array panel of claim 5 , wherein the overpass has first and second edges substantially parallel to the first and the second minor edges, respectively.
9. The thin film transistor array panel of claim 5 , wherein the pixel electrode has a cutout.
10. The thin film transistor array panel of claim 5 , wherein the first major edge of the pixel electrode is substantially parallel to the data line.
11. The thin film transistor array panel of claim 5 , wherein the data line overlaps the pixel electrode.
12. The thin film transistor array panel of claim 11 , wherein the passivation layer comprises organic insulator.
13. The thin film transistor array panel of claim 2 , wherein the overpass is disposed near the obtuse corner of the pixel electrode.