Shift registrer and driving method thereof

1. A shift register having a plurality of stages for shifting a start pulse and outputting a shifted start pulse to a next stage, each of said plurality of stages comprising:

a pull-up transistor controlled by a first node to apply a first clock signal to an output line;

a pull-down transistor controlled by a second node to apply a first driving voltage to the output line;

a controller for controlling the first and second nodes; and

a compensating circuit connected to the first node, the compensating circuit selectively applying the first driving voltage to the first node based on a voltage at a third node, wherein the voltage at the third node is controlled based on the first node.

2. The shift register according to claim 1 , wherein the compensating circuit includes:

a first compensating transistor control by a second driving voltage to apply the first clock signal to the third node;

a second compensating transistor controlled by a voltage at the third node to apply the first driving voltage to the first node; and

a third compensating transistor controlled by a voltage at the first node to apply the first driving voltage to the third node.

3. The shift register according to claim 1 , wherein the compensating circuit includes:

a first compensating transistor controlled by the first clock signal to apply a second driving signal to the third node;

a second compensating transistor controlled by a voltage at the third node to apply the first driving voltage to the first node; and

a third compensating transistor controlled by a voltage at the first node to apply the first driving voltage to the third node.

4. The shift register according to claim 1 , wherein the compensating circuit includes:

a first compensating transistor controlled by the first clock signal to apply the first clock signal to the third node;

a second compensating transistor controlled by a voltage at the third node to apply the first driving voltage to the first node; and

a third compensating transistor controlled by a voltage at the first node to apply the first driving voltage to the third node.

5. A shift register having a plurality of stages for shifting a start pulse and outputting a shifted start pulse to a next stage, each of said plurality of stages comprising:

a pull-up transistor controlled by a first node to apply a first clock signal to an output line;

a pull-down transistor controlled by a second node to apply a first driving voltage to the output line;

a controller for controlling the first and second nodes; and

a compensating circuit connected to the first node, the compensating circuit selectively applying the first driving voltage to the first node based on a voltage at a third node, wherein the compensating circuit selectively prevents the first node from being floated.

6. The shift register according to claim 5 , wherein the compensating circuit applies the first driving voltage to the first node when the first node is floated.

7. A method of driving a shift register having a plurality of stages for shifting a start pulse and outputting a shifted start pulse to a next stage, each of said plurality of stages including a pull-up transistor controlled by a first node to apply a first clock signal to an output line, a pull-down transistor controlled by a second node to apply a first driving voltage to the output line, a controller for controlling the first and second nodes, and a compensating circuit connected to the first node, comprising:

selectively applying the first driving voltage to the first node by the compensating circuit based on a voltage at a third node, wherein the voltage at the third node is controlled based on the first node.

8. A method of driving a shift register having a plurality of stages for shifting a start pulse and outputting a shifted start pulse to a next stage, each of said plurality of stages including a pull-up transistor controlled by a first node to apply a first clock signal to an output line, a pull-down transistor controlled by a second node to apply a first driving voltage to the output line, a controller for controlling the first and second nodes, and a compensating circuit connected to the first node, comprising:

selectively applying the first driving voltage to the first node by the compensating circuit based on a voltage at a third node, wherein the first driving voltage is selectively applied to the first node to prevent the first node from being floated.

9. The method of driving a shift register according to claim 8 , wherein the step of selectively applying the first driving voltage to the first node is performed when the first node is floated.

10. A driving device for a liquid crystal display panel device, comprising:

a shift register having a plurality of stages for shifting a start pulse and outputting a shifted start pulse to a next stage, each of said plurality of stages comprising:

a pull-up transistor controlled by a first node to apply a first clock signal to an output line;

a pull-down transistor controlled by a second node to apply a first driving voltage to the output line;

a controller for controlling the first and second nodes; and

a compensating circuit connected to the first node, the compensating circuit selectively applying the first driving voltage to the first node based on a voltage at a third node, wherein the voltage at the third node is controlled based on the first node.

11. The driving device according to claim 10 , wherein the shift register is formed on a glass substrate.

12. The driving device according to claim 10 , wherein the output line of each of the plurality of stages is connected to a gate line of a liquid crystal display panel.