Array substrate for liquid crystal display device and fabricating method thereof
View Patent ↗A semiconductor device includes a substrate having source and drain regions, a gate insulating layer on the substrate, a gate electrode on the gate insulating layer, an interlayer on the gate electrode, a source electrode connected to the source region, and a drain electrode connected to the drain region, wherein at least one of the gate electrode, the source electrode and the drain electrode includes a first metal layer of molybdenum (Mo)-titanium (Ti) alloy, a second metal layer of one of metallic metals including copper (Cu), aluminum (Al), silver (Ag) and gold (Au) on the first metal layer.
1. An array substrate for a liquid crystal display device, comprising:
a gate pattern on a substrate, the gate pattern including a gate electrode and a gate line;
a gate insulating layer on the gate pattern;
a semiconductor layer on the gate insulating layer;
a data pattern over the semiconductor layer, the data pattern including source and drain electrodes, and a data line;
a passivation layer on the data pattern; and
a pixel electrode connected to the drain electrode and located on the passivation layer,
wherein at least one of the gate pattern and the data pattern includes a first metal layer of molybdenum (Mo)-titanium (Ti) alloy and a second metal layer of one of copper (Cu), aluminum (Al), silver (Ag) and gold (Au) on the first metal layer, wherein the second metal layer is substantially covered by a diffusion layer which has Ti of the first metal layer.
2. The substrate according to claim 1 , wherein the first metal layer acts as a barrier layer for the second metal layer.
3. The substrate according to claim 1 , wherein the pixel electrode includes a transparent conductive material.
4. The substrate array to claim 3 , wherein the transparent conductive materials include one of indium tin oxide (ITO), indium zinc oxide (IZO) and indium tin zinc oxide (ITZO).
5. The substrate according to claim 1 , further comprising a gate pad formed of the same material as the gate pattern.
6. The substrate according to claim 1 , further comprising a data pad formed of the same material as the data pattern.
7. The substrate according to claim 1 , wherein at least one of the gate insulating layer and the passivation layer includes an inorganic insulating material.
8. The substrate according to claim 7 , wherein the inorganic insulating material includes one of silicon nitride (SiNx) and silicon oxide (SiO 2 ).
9. The substrate according to claim 1 , wherein a Ti content of the Mo—Ti alloy is in a range of about 10% to about 90% by atomic weight.
10. A fabricating method of an array substrate for a liquid crystal display device, comprising:
forming a gate pattern on a substrate, the gate pattern including a gate electrode and a gate line;
forming a gate insulating layer on the gate pattern;
forming a semiconductor layer on the gate insulating layer;
forming a data pattern over the semiconductor layer, the data pattern including source and drain electrodes and a data line;
forming a passivation layer on the data pattern; and
forming a pixel electrode connected to the drain electrode and being located on the passivation layer,
wherein the step of forming at least one of the gate pattern and the data pattern includes forming a first metal layer including molybdenum (Mo)-titanium (Ti) alloy and forming a second metal layer including one of copper (Cu), aluminum (Al), silver (Ag) and gold (Au) on the first metal layer, wherein the second metal layer is substantially covered by a diffusion layer which has Ti diffused from the first metal layer.
11. The method according to claim 10 , wherein the diffusion layer is formed by a heat treatment process.
12. The method according to claim 10 , further comprising forming a data pad formed of the same material as the data pattern.
13. The method according to claim 10 , further comprising forming a gate pad formed of the same material as the gate pattern.
14. The method according to claim 10 , wherein the first metal layer acts as a barrier layer for the second metal layer.
15. The method according to claim 10 , wherein a Ti content of the Mo—Ti alloy is in a range of about 10% to about 90% by atomic weight.
16. A semiconductor device, comprising:
a substrate having source and drain regions;
a gate insulating layer on the substrate;
a gate electrode on the gate insulating layer;
an interlayer on the gate electrode;
a source electrode connected to the source region; and
a drain electrode connected to the drain region,
wherein at least one of the gate electrode, the source electrode and the drain electrode includes a first metal layer of molybdenum (Mo)-titanium (Ti) alloy, a second metal layer of one of metallic metals including copper (Cu), aluminum (Al), silver (Ag) and gold (Au) on the first metal layer, wherein the second metal layer is substantially covered by a diffusion layer which has Ti of the first metal layer.
17. The device according to claim 16 , wherein a Ti content of the Mo—Ti alloy is within a range of about 10% to about 90% by atomic weight.
18. A fabricating method of a semiconductor device, comprising:
forming a gate insulating layer on the substrate having source and drain regions;
forming a gate electrode on the gate insulating layer;
forming an interlayer on the gate electrode;
forming a source electrode connected to the source region; and
forming a drain electrode connected to the drain region,
wherein at least one of the gate electrode, the source electrode and the drain electrode includes a first metal layer of molybdenum (Mo)-titanium (Ti) alloy, a second metal layer of one of metallic metals including copper (Cu), aluminum (Al), silver (Ag) and gold (Au) on the first metal layer, wherein the second metal layer is substantially covered by a diffusion layer which has Ti diffused from the first metal layer.
19. The method according to claim 18 , wherein a Ti content of the Mo—Ti alloy is within a range of about 10% to about 90% by atomic weight.