Thin film transistor array substrate and fabricating method thereof

1. A thin film transistor array substrate, comprising:

a gate line and a data line on a substrate to define a pixel area;

a thin film transistor in the pixel area;

a pixel electrode connected to the thin film transistor; and

a common electrode positioned to oppose the pixel electrode and forming a plurality of columns and rows of closed aperture areas for transmitting and shutting off light by a rotation of liquid crystal positioned within said aperture areas,

wherein the pixel electrode and the common electrode are configured such that an electric field between the pixel electrode and the common electrode in a first aperture area is substantially symmetric to an electric field between the pixel electrode and the common electrode in a second aperture area, wherein the first and second aperture areas include at least one of an acute or obtuse angle, and

wherein the pixel electrode includes a plurality of horizontal parts parallel to the gate line and a vertical part connected to the plurality of horizontal parts and parallel to the data line.

2. The thin film transistor array substrate according to claim 1 , wherein a first angle between two sides of one of the pixel electrode and the common electrode is greater than 90 degrees.

3. The thin film transistor array substrate according to claim 2 , wherein a second angle between two sides of an other one of the pixel electrode and the common electrode is greater than 90 degrees.

4. The thin film transistor array substrate according to claim 3 , wherein the angle is greater than 90 degrees and less than 150 degrees.

5. The thin film transistor array substrate according to claim 1 , wherein a first angle between two sides of one of the pixel electrode and the common electrode is less than 90 degrees.

6. The thin film transistor array substrate according to claim 5 , wherein a second angle between two sides of an other one of the pixel electrode and the common electrode is less than 90 degrees.

7. The thin film transistor array substrate according to claim 6 , wherein an angle is less than 90 degrees and greater than 30 degrees.

8. The thin film transistor array substrate according to claim 1 , wherein an angle between one of the horizontal parts and the vertical part is greater than 90 degrees and less than 150 degrees.

9. The thin film transistor array substrate according to claim 1 , wherein an angle between the one of the horizontal parts and the vertical part is less than 90 degrees and greater than 30 degrees.

10. The thin film transistor array substrate according to claim 1 , wherein the common electrode includes:

first and second vertical parts parallel to the data line; and

a horizontal part between the first and second vertical parts and parallel to the gate line.

11. The thin film transistor array substrate according to claim 10 , wherein an angle between the horizontal part and one of the first and second vertical parts is greater than 90 degrees and less than 150 degrees.

12. The thin film transistor array substrate according to claim 10 , wherein an angle between the horizontal part and one of the first and second vertical parts is less than 90 degrees and greater than 30 degrees.

13. The thin film transistor array substrate according to claim 1 , wherein the maximum rotation angle of each center of the aperture areas is greater than 45 degrees.

14. A thin film transistor array substrate, comprising:

a plurality of aperture areas having a tetragonal shape in a pixel area defined between a gate line and a data line,

a pixel electrode and a common electrode positioned in the pixel area defining at least first and second aperture areas; and

wherein at least one corner angle of the first and second aperture areas is different from other corner angles, wherein the pixel electrode and the common electrode are configured such that an electric field between the pixel electrode and the common electrode in the first aperture area is substantially symmetric to an electric field between the pixel electrode and the common electrode in the second aperture area, and

wherein the pixel electrode includes a plurality of horizontal parts parallel to the gate line and a vertical part connected to the plurality of horizontal parts and parallel to the data line.

15. The thin film transistor array substrate according to claim 14 , wherein an angle between two sides of one of the pixel electrode and the common electrode is either less than 90 degrees or greater than 90 degrees.

16. The thin film transistor array substrate according to claim 15 , wherein the angle is greater than 90 degrees and less than 150 degrees.

17. The thin film transistor array substrate according to claim 15 , wherein the angle is less than 90 degrees and greater than 30 degrees.

18. The thin film transistor array substrate according to claim 14 , wherein the maximum rotation angle of at least one of the plurality of aperture areas is greater than 45 degrees.

19. A method of fabricating a thin film transistor array substrate, comprising the steps of:

forming a gate line and a data line on a substrate to define a pixel area;

forming a thin film transistor in the pixel area;

forming a pixel electrode connected to the thin film transistor; and

forming a common electrode positioned to oppose the pixel electrode to form columns and rows of closed aperture areas for transmitting and shutting off light by a rotation of liquid crystal positioned within the pixel area, wherein a first aperture area has a substantially symmetric electric field to a second aperture area, wherein the aperture areas include at least one of an acute or obtuse angle,

wherein the step of forming the pixel electrode includes forming a plurality of horizontal parts parallel to the gate line and a vertical part connected to the plurality of horizontal parts and parallel to the data line.

20. The method according to claim 19 , wherein an angle between one of the horizontal parts and the vertical part is greater than 90 degrees and less than 150 degrees.

21. The method according to claim 19 , wherein the angle between one of the horizontal parts and the vertical part is less than 90 degrees and greater than 30 degrees.

22. The method according to claim 19 , wherein the step of forming the common electrode includes:

first and second vertical parts parallel to the data line; and

a horizontal part between the first and second vertical parts and parallel to the gate line.

23. The method according to claim 22 , wherein an angle between the horizontal part and one of the vertical parts is greater than 90 degrees and less than 150 degrees.

24. The method according to claim 22 , wherein an angle between the horizontal part and one of the vertical parts is less than 90 degrees and greater than 30 degrees.

25. The method of claim 19 , wherein the maximum rotation angle of each center of the aperture areas is greater than 45 degrees.

26. A method of fabricating a thin film transistor array substrate, comprising the steps of:

forming a gate line and a data line on a substrate to define a pixel area;

forming a thin film transistor in the pixel area;

forming a pixel electrode connected to the thin film transistor; and

forming a common electrode positioned to oppose the pixel electrode to form first and second closed aperture areas for transmitting and shutting off light by a rotation of liquid crystal positioned within the pixel area, the common electrode including first and second vertical parts parallel to the data line, the common electrode further including a horizontal part between the first and second vertical parts and parallel to the gate line, wherein an angle between the horizontal part and one of the vertical parts is less than 90 degrees and greater than 30 degrees,

wherein the first aperture area has a substantially symmetric electric field to the second aperture area, wherein the aperture areas include at least one of an acute or obtuse angle.