IP Library Granted Patent US 7,395,483
Granted Patent B1
US 7,395,483 · App. 10/966,083 · Granted Jul 1, 2008

Method and apparatus for performing error-detection and error-correction

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Quick Facts
Patent No.
US 7,395,483
App. No.
10/966,083
Granted
Jul 1, 2008
Kind
B1
Abstract

One embodiment of the present invention provides a system that facilitates detecting and correcting errors. The system operates by receiving a data packet comprised of p words on a communication pathway, wherein each bit of a word is received on a separate data line in a set of data lines that comprise the communication pathway. The system also receives a time signature t on the communication pathway, wherein t contains per-bit error information for the p words in the data packet. As the data packet is received, the system performs an error-detection operation on each data bit of the data packet in parallel, wherein the error-detection operation generates per-bit error information for each bit position across the p words in the data packet. Finally, the system compares the generated per-bit error-information with the corresponding per-bit error information in the time signature t to determine if there exists an error.

Claims (32)

1. A method for performing error-detection and/or error-correction, comprising:

receiving a data packet comprised of p words on a communication pathway, wherein each bit of a word is received on a separate data line in a set of data lines that comprise the communication pathway;

receiving a time signature t on the communication pathway, wherein t contains per-bit error information for the p words in the data packet; and

performing an error-detection operation on each data bit of the data packet in parallel, wherein the error-detection operation generates per-bit error information for each bit position across the p words in the data packet; and

comparing the generated per-bit error-information with the corresponding per-bit error information in the time signature t to detect and/or correct errors in the data packet.

2. The method of claim 1 , further comprising forwarding the data packet and the time signature t to a destination along with an error flag e, wherein e contains per-bit error indication information which indicates errors for corresponding bit-positions for the p words in the data packet.

3. The method of claim 1 , wherein each of the p words in the data packet includes a traditional word-based error-detection code, which is transmitted on separate data lines in the set of data lines, and wherein the method further comprises:

performing traditional word-based error-detection on the p words in the data packet to determine if there is an error in a word in the p words; and

if a word is determined to have an error, using the per-bit error indication information to determine the position of an incorrect bit in the word.

4. The method of claim 1 , wherein time signature t comprises multiple consecutive words on the data channel.

5. The method of claim 1 , further comprising

dividing the packet into a plurality of sub-packets;

generating time signatures t n for each of the sub-packets; and

interleaving time signatures t n between the sub-packets when the packet is forwarded to a destination.

6. The method of claim 2 , wherein the per-bit error indication information in error flag e is stored in a bit position other than the bit position which the error indication information is calculated for to facilitate indicating a “stuck-at” fault on a data line which is different than a data line upon which the “stuck-at” fault arises.

7. The method of claim 2 , wherein error flag e is only sent when errors are detected.

8. An apparatus for performing error-detection and/or error-correction, comprising:

a receiving mechanism configured to receive a data packet comprised of p words on a communication pathway, wherein each bit of a word is received on a separate data line in a set of data lines that comprise the communication pathway;

wherein the receiving mechanism is additionally configured to receive a time signature t on the communication pathway, wherein t contains per-bit error information for the p words in the data packet; and

a detection mechanism configured to perform an error-detection operation on each data bit of the data packet in parallel, wherein the error-detection operation generates per-bit error information for each bit position across the p words in the data packet; and

a comparison mechanism configured to compare the generated per-bit error-information with the corresponding per-bit error information in the time signature t to detect and/or correct errors in the data packet.

9. The apparatus of claim 8 , further comprising a forwarding mechanism configured to forward the data packet and the time signature t to a destination along with an error flag e, wherein e contains per-bit error indication information which indicates errors for corresponding bit-positions for the p words in the data packet.

10. The apparatus of claim 8 , wherein each of the p words in the data packet includes a traditional word-based error-detection code, which is transmitted on separate data lines in the set of data lines, and wherein the apparatus further comprises:

a traditional detection mechanism configured to perform traditional word-based error-detection on the p words in the data packet to determine if there is an error in a word in the p words; and

wherein if a word is determined to have an error, the comparison mechanism is further configured to use the per-bit error indication information to determine the position of an incorrect bit in the word.

11. The apparatus of claim 8 , wherein time signature t comprises multiple consecutive words on the data channel.

12. The apparatus of claim 8 , further comprising

a division mechanism configured to divide the packet into a plurality of sub-packets;

a generating mechanism configured to generate time signatures t n for each of the sub-packets; and

an interleaving mechanism configured to interleave time signatures t n between the sub-packets when the packet is forwarded to a destination.

13. The apparatus of claim 9 , wherein the forwarding mechanism is further configured to store the per-bit error indication information in error flag e in a bit position other than the bit position which the error indication information is calculated for to facilitate indicating a “stuck-at” fault on a data line which is different than a data line upon which the “stuck-at” fault arises.

14. The apparatus of claim 9 , wherein error flag e is only sent when errors are detected.

Assignments (2)
MERGER AND CHANGE OF NAME Recorded Dec 16, 2015
From: ORACLE USA, INC.; SUN MICROSYSTEMS, INC.; ORACLE AMERICA, INC.
To: ORACLE AMERICA, INC.
Reel/Frame 037303/0336 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2004
From: TOURANCHEAU, BERNARD; HO, RONALD; DROST, ROBERT J.
To: SUN MICROSYSTEMS, INC.
Reel/Frame 015904/0638 →