Single chip stereo imaging system with dual array design
A stereo imaging chip is presented that contains two imaging arrays located at opposite edges of the chip. Support circuitry, including a computational unit, is located on the chip in areas not occupied by the imaging arrays. A FPGA located on the chip is used to provide instructions to the computational unit and allow updates. A stereo focusing unit on a single optical substrate focuses a distant object onto the two imaging arrays. The semiconductor process producing the chip provides accurate alignment of the two imaging arrays and the use of a single optical substrate to containing the stereo lens provides additional dimensional accuracy and stability to allow calculations of the distance to distant objects.
1 . A stereo imaging system, comprising:
a) a semiconductor chip,
b) a first imaging array,
c) a second imaging array,
d) said first and second imaging arrays located at opposite edges of said chip with support circuits and a computational unit located in areas on said chip not used by the imaging arrays to form a stereo imaging chip.
2 . The system of claim 1 , wherein said first and second imaging arrays comprise rows and columns of light sensitive elements called pixels.
3 . The system of claim 1 , wherein said first and second image arrays are positioned as far apart as permitted by said chip.
4 , The system of claim 1 , wherein said first and second image arrays located on said chip provide a relative alignment determined by a semiconductor process creating said chip.
5 . The system of claim 4 , wherein said first and second image arrays are within a same reticule of the semiconductor process, whereby the image arrays can be placed onto said imaging chip without stitching circuitry between said image arrays.
6 . The system of claim 1 , wherein said support circuits further comprise:
a) regulators to regulate power to circuitry on said chip,
b) a clock to regulate the timing of circuitry on said chip.
c) an analog signal chain to couple analog pixel data from said first and second imaging arrays to said support circuits,
d) an analog to digital converter (ADC) to couple said analog pixel data to said computational unit.
7 . the system of claim 6 , wherein said supports circuits include a field programmable array (FPGA) to allow modification of instructions for the operations of the stereo imaging chip.
8 . The system of claim 1 , wherein said computational unit is a digital signal processor (DSP).
9 . The system of claim 1 , wherein said computational unit is formed from synthesized logic
10 . The system of claim 1 , further comprising a stereo focusing unit is positioned external to said chip to focus distant objects onto said first and second imaging arrays.
11 . The system of claim 10 , wherein said stereo focusing unit further comprises two lenses, whereby a first lens focuses said distant objects onto said first imaging array and a second lens focuses said distant objects onto said second imaging array.
12 . The system of claim 10 , wherein said two lenses are integrated together into a single optical substrate to form said stereo focusing unit.
13 . The system of claim 10 , wherein said computational unit analyzes a first image captured by the first imaging array and a second image captured by the second imaging array to calculate a distance to said distant objects.
14 . The system of claim 13 , wherein said computational unit determines a position of a first distant object relative to a second distant object of said distant objects.
15 . The system of claim 13 , wherein said computational unit outputs a stereo image of said distant objects.
16 . The system of claim 15 , wherein said stereo image is a digital stereo image.
17 . The system of claim 15 , wherein said computational unit controls said support circuitry to output a stereo video of said distant objects.
18 . The system of claim 17 , wherein said stereo video is in a digital format.
19 . A method of stereo imagery, comprising:
a) forming a first image array on a semiconductor chip,
b) forming a second image array on said chip,
c) positioning said first and second image arrays at opposite edges of said chip,
d) forming support circuitry and a computational unit in areas on said chip not occupied by said first and second image arrays,
e) placing a stereo lens between said chip and a distant object,
f) capturing an image of said distant object with the first and second image arrays,
g) performing calculations on pixels of the first and second image array with a computational unit contained on said chip.
20 . The method of claim 19 , wherein said first and second image arrays are light sensitive arrays containing rows and columns of pixels.
21 . The method of claim 19 , wherein positioning said first and second image arrays at opposite edges of the chip provide a maximum separation of said image arrays on said chip.
22 . The method of claim 19 , wherein said support circuitry further comprise:
a) regulators to regulate power to circuitry on said chip,
b) a clock to regulate the timing of circuitry on said chip.
c) an analog signal chain to couple analog pixel data from said first and second imaging arrays to said support circuits,
d) an analog to digital converter (ADC) to couple said analog pixel data to said computational unit.
23 . The method of claim 22 , wherein said supports circuits include a field programmable array (FPGA) to allow modification of instructions for the operations of the stereo imaging chip.
24 . The method of claim 19 , wherein said computational unit is formed from synthesized logic.
25 . The method of claim 19 , wherein said computational unit is a digital signal processor (DSP).
26 . The method of claim 19 , wherein said stereo lens further comprises two lenses, whereby a first lens focuses said distant object onto said first image array and a second lens focuses said distant object onto said second image array.
27 . The method of claim 26 , wherein said two lenses are integrated together into a single optical substrate.
28 . The system of claim 19 , wherein said computational unit is used to analyze a first image captured by the first imaging array and a second image captured by the second imaging array to determine a distance to said distant objects.
29 . The system of claim 19 , wherein said computational unit determines a position of a first distant object relative to a second distant object of said distant objects.
30 . The system of claim 19 , wherein said computational unit outputs a stereo image of said distant objects.
31 . The system of claim 30 , wherein said stereo image is a digital stereo image.
32 . The system of claim 19 , wherein said computational unit controls said support circuitry to output a stereo video of said distant objects.
33 . The system of claim 32 , wherein said stereo video is in a digital format.