Reducing probe traffic in multiprocessor systems
View Patent ↗A computer system having a plurality of processing nodes interconnected by a first point-to-point architecture is described. Each processing node has a cache memory associated therewith. A probe filtering unit is operable to receive probes corresponding to memory lines from the processing nodes and to transmit the probes only to selected ones of the processing nodes with reference to probe filtering information. The probe filtering information is representative of states associated with selected ones of the cache memories.
1. A computer system comprising a plurality of processing nodes interconnected by a first point-to-point architecture, each processing node having a cache memory associated therewith, the computer system further comprising a probe filtering unit which is operable to receive probes corresponding to memory lines from the processing nodes and to transmit the probes only to selected ones of the processing nodes with reference to probe filtering information representative of states associated with selected ones of the cache memories.
2. The computer system of claim 1 wherein the probe filtering unit corresponds to an additional node interconnected with the plurality of processing nodes via the first point-to-point architecture.
3. The computer system of claim 2 wherein the additional node comprises a cache coherence controller, and the probe filtering information comprises a cache coherence directory which includes entries corresponding to memory lines stored in the selected cache memories.
4. The computer system of claim 1 wherein the plurality of processing nodes comprises a first cluster of processors, the computer system comprising a plurality of clusters of processors including the first cluster, the plurality of clusters being interconnected via a second point-to-point architecture.
5. The computer system of claim 4 further comprising a cache coherence controller on the first point-to-point architecture which is operable to facilitate interconnection of the first cluster with others of the plurality of clusters via the second point-to-point architecture.
6. The computer system of claim 5 wherein the cache coherence controller comprises the probe filtering unit, and the probe filtering information comprises a cache coherence directory.
7. The computer system of claim 1 wherein the first point-to-point architecture comprises a HyperTransport architecture.
8. The computer system of claim 1 wherein each of the processing nodes is operable to transmit the probes only to the probe filtering unit.
9. The computer system of claim 8 wherein each of the processing nodes has at least one routing table associated therewith which governs which portions of the first point-to-point architecture the associated processing node employs for communicating with others of the processing nodes, the at least one routing table in each of the processing nodes being configured to direct all of the probes to the probe filtering unit.
10. The computer system of claim 9 wherein the at least one routing table in each of the processing nodes is configured to direct all broadcasts to the probe filtering unit.
11. The computer system of claim 1 wherein each of the processing nodes is programmed to complete a memory transaction after receiving a first number of responses to a first probe, the first number being fewer than the number of processing nodes.
12. The computer system of claim 11 wherein the probe filtering unit has temporary storage associated therewith for holding read response data from one of the cache memories, and the first number is one.
13. The computer system of claim 11 wherein the probe filtering unit is operable to forward read response data to a requesting node before accumulating all probe responses associated with the memory transaction, and the first number is two.
14. The computer system of claim 1 wherein the probe filtering unit is further operable to modify the probes such that the selected processing nodes transmit responses to the probes to the probe filtering unit.
15. The computer system of claim 1 wherein the probe filtering unit is operable to accumulate responses to each probe, and respond to requesting nodes in accordance with the accumulated responses.
16. A probe filtering unit for use in a computer system comprising a plurality of processing nodes interconnected by a first point-to-point architecture, each processing node having a cache memory associated therewith, the probe filtering unit being operable to receive probes corresponding to memory lines from the processing nodes and to transmit the probes only to selected ones of the processing nodes with reference to probe filtering information representative of states associated with selected ones of the cache memories.
17. An integrated circuit comprising the probe filtering unit of claim 16 .
18. The integrated circuit of claim 17 wherein the integrated circuit comprises an application-specific integrated circuit.
19. At least one computer-readable medium having data structures stored therein representative of the probe filtering unit of claim 16 .
20. The at least one computer-readable medium of claim 19 wherein the data structures comprise a simulatable representation of the probe filtering unit.
21. The at least one computer-readable medium of claim 20 wherein the simulatable representation comprises a netlist.
22. The at least one computer-readable medium of claim 19 wherein the data structures comprise a code description of the probe filtering unit.
23. The at least one computer-readable medium of claim 22 wherein the code description corresponds to a hardware description language.
24. A set of semiconductor processing masks representative of at least a portion of the probe filtering unit of claim 16 .
25. A computer implemented method for reducing probe traffic in a computer system comprising a plurality of processing nodes interconnected by a first point-to-point architecture, each processing node having a cache memory associated therewith, the method comprising:
transmitting a probe from a first one of the processing nodes only to a probe filtering unit, the probe corresponding to a memory line;
evaluating the probe with the probe filtering unit to determine whether a valid copy of the memory line is in any of the cache memories, the evaluating being done with reference to probe filtering information associated with the probe filtering unit and representative of states associated with selected ones of the cache memories;
transmitting the probe from the probe filtering unit only to selected ones of the processing nodes identified by the evaluating;
accumulating probe responses from the selected processing nodes with the probe filtering unit; and
responding to the probe from the first processing node only with the probe filtering unit.