Dual-PLL signaling for maintaining synchronization in a communications system
View Patent ↗A communications management system introduces a low bandwidth phase locked loop (LoBW-PLL) working in tandem with a high bandwidth phase locked loop (HiBW-PLL). The LoBW-PLL only needs to follow the average frequency of the transported clock and not all of the excursions made by the master clock. During periods of downstream outage, the LoBW-PLL opens its loop and free wheels such that disturbances caused by a reacquisition do not impact the concept of time for the LoBW-PLL. After reacquisition, the LoBW-PLL and HiBW-PLL are compared to determine if a timing error has occurred. If a timing error is detected, the magnitude of the timing error is measured upon completion of the reacquisition cycle, and this measurement is used to correct the timing error.
1. A method of correcting a timing error within a communications system, comprising:
detecting a downstream outage;
initiating an acquisition cycle to recover a clock transport quantity from a downstream channel in response to detecting a downstream outage;
determining a first clock difference from a first high bandwidth clock and a first low bandwidth clock, wherein said first high bandwidth clock and said first low bandwidth clock are recovered from said downstream channel using a phase locked loop (PLL);
upon completion of said acquisition cycle, determining a final clock difference from a subsequent high bandwidth clock and a subsequent low bandwidth clock, wherein said subsequent high bandwidth clock and said subsequent low bandwidth clock are recovered from said downstream channel using a PLL;
determining a timing difference from said first clock difference and said final clock difference; and
applying said timing difference to correct the timing error.
2. The method according to claim 1 , wherein said detecting comprises:
detecting a loss of clock transport information on said downstream channel.
3. The method according to claim 1 , further comprising:
determining at least one of said first clock difference and said final clock difference from an up/down counter.
4. The method according to claim 1 , wherein said determining a timing difference comprises:
computing a clock drift from said first clock difference and said final clock difference, whereby said clock drift is applied to determine said timing difference.
5. The method according to claim 1 , wherein said determining a timing difference comprises:
applying a frequency of a low bandwidth clock to determine said timing difference.
6. The method according to claim 1 , wherein said applying comprises:
offsetting an accumulator of a numerically controlled oscillator to correct the timing error.
7. The method according to claim 1 , wherein said applying comprises:
correcting symbol timing.
8. The method according to claim 1 , wherein said applying comprises:
correcting burst timing.
9. The method of claim 1 , wherein the first high bandwidth clock is generated from a high bandwidth phase locked loop (PLL) and the first low bandwidth clock is generated from a low bandwidth PLL.
10. The method of claim 9 , further comprising:
upon initiation of the acquisition cycle, opening a loop of the low bandwidth PLL.
11. A method of detecting a timing error within a communications system, comprising:
determining a first clock difference from a first high bandwidth clock and a first low bandwidth clock, wherein said first high bandwidth clock and said first low bandwidth clock are recovered from a downstream channel using a phase locked loop (PLL);
determining a second clock difference from a subsequent high bandwidth clock and a subsequent low bandwidth clock, wherein said subsequent high bandwidth clock and said subsequent low bandwidth clock are recovered from said downstream channel using a PLL; and
detecting an occurrence of a timing error from a magnitude of the difference between said first clock difference and said second clock difference.
12. The method according to claim 11 , further comprising:
applying said magnitude to correct said timing error.
13. A system for detecting a timing error within a communications system, comprising:
a receiver configured to recover a clock transport quantity from a downstream channel;
a high bandwidth phase lock loop communicatively coupled to said receiver and configured to access said clock transport quantity to recover a high bandwidth clock;
a low bandwidth phase lock loop communicatively coupled to said receiver and configured to access said clock transport quantity to recover a low bandwidth clock; and
a clock comparator configured to determine a first clock difference from said high bandwidth clock and said low bandwidth clock, a second clock difference from said high bandwidth clock and said low bandwidth clock, and a timing difference from said first clock difference and said second clock difference.
14. The system of claim 13 , further comprising:
a processor communicatively coupled to a clock comparator and configured to detect a timing error from an output from said clock comparator.
15. The system of claim 13 , further comprising:
a processor configured to determine an offset value from an output from a clock comparator, wherein said offset value is applied to correct a timing error.
16. The system of claim 13 , further comprising:
a processor communicatively coupled to said receiver and adapted to initiate an acquisition cycle to recover a clock transport quantity from said downstream channel, wherein said acquisition cycle is initiated in response to a downstream outage.