Low power, high SNR, high order delta sigma modulator stage having integrators with pipelined cross coupled input circuits

1. A delta sigma modulator, comprising:

a first integrator having a first cross coupled switched capacitor sampling network with an input capable of receiving an analog signal;

a second integrator coupled to said first integrator and having a second cross coupled switched capacitor sampling network; and

a quantizer coupled to said second integrator and having a first output capable of producing a modulated signal;

wherein said first integrator samples during a first phase of a clock and both samples and integrates during a second phase of said clock and said second integrator both samples and integrates during said first phase and samples during said second phase.

2. The delta sigma modulator of claim 1 , wherein said first and said second cross coupled switched capacitor sampling networks are configured as differential circuits.

3. The delta sigma modulator of claim 1 , wherein said first and said second cross coupled switched capacitor networks include a reference voltage that is less than an average of two power supply voltages for the delta sigma modulator.

4. The delta sigma modulator of claim 1 , wherein during said first phase, a set of switches in said first cross coupled switched capacitor sampling network is closed while contemporaneously a corresponding set of switches in said second cross coupled switched capacitor sampling network is opened.

5. The delta sigma modulator of claim 1 , wherein each of said first and said second cross coupled switched capacitor sampling networks comprises:

a sampling capacitor having a first terminal and a second terminal, said first terminal coupled to an input of a corresponding cross coupled switched capacitor sampling network of said first and said second cross coupled switched capacitor sampling networks;

a first summing junction switch having a third terminal and a fourth terminal, said third terminal coupled to said second terminal;

an operational amplifier having a fifth terminal coupled to said fourth terminal; and

a second summing junction switch having a sixth terminal and a seventh terminal, said sixth terminal coupled to said second terminal, said seventh terminal coupled to a reference voltage, wherein said reference voltage is less than an average of two power supply voltages for the delta sigma modulator.

6. The delta sigma modulator of claim 5 , wherein said first and said second summing junction switches are metal oxide semiconductor field effect transistors.

7. The delta sigma modulator of claim 6 , wherein, for a given resistance of said second summing junction switch, a size of said second summing junction switch is a function of said reference voltage.

8. The delta sigma modulator of claim 1 , wherein said first cross coupled switched capacitor sampling network includes a digital-to-analog converter.

9. The delta sigma modulator of claim 8 , wherein said digital-to-analog converter is configured as a cross coupled feedback switched capacitor network.

10. The delta sigma modulator of claim 9 , wherein said cross coupled feedback switched capacitor network is coupled to a reference signal voltage, said reference signal voltage is equal to one of two power supply voltages for the delta sigma modulator.

11. The delta sigma modulator of claim 1 , wherein said second cross coupled switched capacitor sampling network includes a digital-to-analog converter.

12. The delta sigma modulator of claim 11 , wherein said digital-to-analog converter is configured as a cross coupled feedback switched capacitor network.

13. The delta sigma modulator of claim 12 , wherein said cross coupled feedback switched capacitor network is coupled to a reference signal voltage, said reference signal voltage is equal to one of two power supply voltages for the delta sigma modulator.

14. The delta sigma modulator of claim 12 , wherein said quantizer has a second output capable of producing an inverse modulated signal.

15. The delta sigma modulator of claim 14 , wherein switches in said cross coupled feedback switched capacitor network are further controlled by said modulated signal and said inverse modulated signal.

16. A delta sigma modulator, comprising:

a first differential integrator having a first cross coupled switched capacitor sampling network with an input capable of receiving an analog signal;

a second differential integrator coupled to said first differential integrator and having a second cross coupled switched capacitor sampling network; and

a quantizer coupled to said second differential integrator and having an output capable of producing a modulated signal.

17. The delta sigma modulator of claim 16 , wherein a first processing delay between said first and said second differential integrators is half of a cycle of a clock, and a second processing delay between said first differential integrator and said quantizer is one-and-a-half of said cycle of said clock.

18. A delta sigma modulator, comprising:

a first integrator having a first cross coupled switched capacitor sampling network with an input capable of receiving an analog signal;

a second integrator coupled to said first integrator;

a quantizer coupled to said second integrator and having an output capable of producing a modulated signal; and

a half period delay buffer coupled between said quantizer and said first integrator.

19. The delta sigma modulator of claim 18 , wherein said second integrator has a second cross coupled switch capacitor sampling network.

20. The delta sigma modulator of claim 19 , wherein said first and said second cross coupled switched capacitor sampling networks are configured as differential circuits.