Vacuum package fabrication of integrated circuit components
View Patent ↗A method for manufacturing integrated circuit device lids includes creating a lid cavity on the surface of a lid wafer, forming a sealing surface on the lid wafer that surrounds the lid cavity, and forming a trench on the lid wafer between the lid cavity and the sealing surface. The resulting structure uptakes excess sealing surface material and prevents such material from entering the lid cavity.
1. A method for manufacturing an integrated circuit device lid, comprising the steps of:
forming at least one lid cavity on a surface of a lid wafer, the lid wafer having a sealing surface;
forming at least one sealing structure on the lid wafer disposed around one of the at least one cavities, each sealing structure including a bonding adhesion structure coupled to the sealing surface of the lid wafer and a bonding layer coupled to the bonding adhesion structure such that the bonding layer is at least substantially separated from the sealing surface of the lid wafer by the bonding adhesion structure; and
forming at least one at least substantially continuous trench in the sealing surface of the lid wafer and disposed around the cavity and between the cavity and the sealing structure, the trench being defined in part by a pair of side walls extending at least substantially continuously around the cavity.
2. The method of claim 1 , wherein the at least one lid cavity is formed by wet or dry isotropic etching.
3. The method of claim 1 , wherein the step of forming at least one lid cavity comprises forming a plurality of lid cavities on the surface of the lid wafer.
4. The method of claim 3 , wherein the step of forming at least one sealing structure comprises forming a plurality of sealing structures on the surface of the lid wafer, each sealing structure disposed around one of the plurality of lid cavities.
5. The method of claim 4 , wherein the step of forming at least one at least substantially continuous trench comprises forming a plurality of at least substantially continuous trenches, each at least substantially continuous trench disposed between one of the sealing surfaces and one of the lid cavities.
6. The method of claim 1 , wherein the at least one at least substantially continuous trench is formed by isotropic wet or dry etching.
7. The method of claim 1 , wherein the at least one at least substantially continuous trench is formed by anisotropic etching.
8. The method of claim 1 , wherein the at least one at least substantially continuous trench is formed with a depth and width that are approximately equal.
9. The method of claim 1 , wherein the depth of the at least one at least substantially continuous trench is determined by the width of a surface opening of the trench.
10. The method of claim 1 , further comprising:
placing the lid wafer below a device wafer so that the bonding layer of the lid wafer faces upward, the device wafer comprising a bonding adhesion structure;
aligning the device wafer over the lid wafer such that the bonding adhesion surface of the device wafer is aligned with the bonding layer of the lid wafer; and
bonding together the device wafer and the lid wafer with the bonding layer of the lid wafer.
11. The method of claim 1 , wherein the bonding layer is a solder layer.
12. The method of claim 1 , wherein the bonding layer is an adhesive.
13. The method of claim 1 , wherein the each of the at least one cavities formed in the lid wafer is operable to receive an integrated circuit device such that at least a portion of the integrated circuit device extends into the cavity.
14. The method of claim 1 , wherein each of the at least one cavities formed in the lid wafer is operable to receive a microelectromechanical systems (MEMS) device such that at least a portion of the MEMS device extends into the cavity.