Resource-limited directories with fine-grained eviction

1. A system comprising:

a memory;

a first processor operatively connected to a first cache;

a second processor operatively connected to a second cache; and

a directory implemented in hardware operatively connected to the first cache, the second cache, and the memory,

wherein the directory comprises at least one location,

wherein the at least one location is configured to store a first entry and a second entry,

wherein the first entry comprises a first address field, a first processor field, and a first state field, and

wherein the first processor field stores a value corresponding to the first processor and a value corresponding to the second processor, if the first address field stores a first physical address and a first cache entry in the first cache is associated with the first physical address and a second cache entry in the second cache is associated with the first physical address.

2. The system of claim 1 , further comprising:

a buffer operatively connected to the directory and configured to store the first entry after the first entry is evicted from the directory.

3. The system of claim 1 , wherein the directory is configured to evict the first entry from the directory and store the first entry in a buffer operatively connected to the directory.

4. The system of claim 1 , wherein the directory is configured to implement a cache-coherency protocol.

5. The system of claim 4 , wherein the cache-coherency protocol comprises at least one selected from the group consisting of a Modified-Shared-Invalid protocol, a Modified-Exclusive-Shared-Invalid protocol, and a Modified-Owned-Exclusive-Shared-Invalid protocol.

6. The system of claim 1 , wherein the directory is located in a memory controller associated with the memory.

7. A system comprising:

a memory;

a first processor operatively connected to a first cache;

a second processor operatively connected to a second cache; and

a directory implemented in hardware operatively connected to the first cache, the second cache, and the memory,

wherein the directory comprises at least one location,

wherein the at least one location is configured to store a first entry and a second entry,

wherein a first physical address associated with a first cache entry in the first cache and a second physical address associated with a second cache entry in the first cache index to the at least one location, and

wherein the first physical address of the first cache entry is stored in a first address field of the first entry, a value corresponding to the first processor is stored in a first processor field of the first entry, the second physical address of the second cache entry is stored in a second address field of the second entry, and the value corresponding to the first processor is stored in a second processor field of the second entry.

8. The system of claim 7 , wherein a first set of low-order bits in the first physical address, and second set of low-order bits in the second physical address are used to index into the at least one location.

9. The system of claim 7 , further comprising:

a buffer operatively connected to the directory and configured to store the first entry after the first entry is evicted from the directory.

10. The system of claim 7 , wherein the directory is configured to evict the first entry from the directory and store the first entry in a buffer operatively connected to the directory.

11. The system of claim 7 , wherein the directory is configured to implement a cache-coherency protocol.

12. The system of claim 11 , wherein the cache-coherency protocol comprises at least one selected from the group consisting of a Modified-Shared-Invalid protocol, a Modified-Exclusive-Shared-Invalid protocol, and a Modified-Owned-Exclusive-Shared-Invalid protocol.

13. The system of claim 7 , wherein the directory is located in a memory controller associated with the memory.

14. A system comprising:

a memory;

a first processor operatively connected to a first cache;

a second processor operatively connected to a second cache; and

a directory implemented in hardware operatively connected to the first cache, the second cache, and the memory,

wherein the directory comprises at least one location,

wherein the at least one location is configured to store a first entry and a second entry,

wherein a first physical address of a first cache entry in the first cache and a second physical address of a second cache entry in the second cache index to the at least one location, and

wherein the first physical address of the first cache entry is stored in a first address field of the first entry, a value corresponding to the first processor is stored in a first processor field of the first entry, the second physical address of the second cache entry is stored in a second address field of the second entry, and a value corresponding to the second processor is stored in a second processor field of the second entry.

15. The system of claim 14 , wherein a first set of low-order bits in the first physical address, and second set of low-order bits in the second physical address are used to index into the at least one location.

16. The system of claim 14 , further comprising:

a buffer operatively connected to the directory and configured to store the first entry after the first entry is evicted from the directory.

17. The system of claim 14 , wherein the directory is configured to evict the first entry from the directory and store the first entry in a buffer operatively connected to the directory.

18. The system of claim 14 , wherein the directory is configured to implement a cache-coherency protocol.

19. The system of claim 18 , wherein the cache-coherency protocol comprises at least one selected from the group consisting of a Modified-Shared-Invalid protocol, a Modified-Exclusive-Shared-Invalid protocol, and a Modified-Owned-Exclusive-Shared-Invalid protocol.

20. The system of claim 14 , wherein the directory is located in a memory controller associated with the memory.