Method for priority scheduling and priority dispatching of store conditional operations in a store queue
View Patent ↗A method, system, and processor chip design for reducing the latency between completing a LARX operation and receiving the associated STCX operation to complete the update to the cache line. Each entry of the store queue of the issuing processor is provided an additional tracking bit (priority bit). The priority bit is set whenever a STCX operation is placed within the entry. During selection of an entry for dispatch by the arbitration logic, the arbitration logic scans the value of the priority bits of each eligible entry. An entry with the priority bit set is given priority in the selection process within architectural rules. That entry is then selected for dispatch as early as is possible within the established rules.
1. In a data processing system having a processors with a processor core, store queue (STQ) mechanism, read claim (RC) mechanism, and associated processor cache, a method for reducing latency of processing store conditional (STCX) operations, said method comprising:
responsive to allocation of a STCX operation to an entry of the store queue, tagging the entry as a higher priority entry relative to a prior entry allocated a regular store operation; and selecting the higher priority entry for dispatch ahead of said prior entry during dispatch selection process, wherein the STCX operation is forwarded to said processor cache ahead of the prior entry, wherein a latency of processing STCX operations is substantially reduced, wherein said selecting step further comprises:
first determining that both said higher priority entry and said prior entry are valid for dispatch;
evaluating when a dispatch of the higher priority entry ahead of the prior entry does not violate a predefined architectural rule for dispatching entries from the store queue; and
dispatching said higher priority entry ahead of said prior entry when a selection of said higher priority entry for dispatch ahead of said prior entry does not violate the predefined architectural rule for dispatching entries from the store queue.
2. The method of claim 1 , wherein said tagging includes setting a priority bit associated with the higher priority entry, wherein the priority bit of the prior entry is not set.
3. The method of claim 2 , further comprising:
reading a value of the priority bit after verifying that an entry is valid for dispatch; and
re-setting a priority bit associated with said higher priority entry when the STCX operation in the higher priority entry is dispatched.
4. The method of claim 1 , further comprising:
receiving said prior store operation within the prior entry of the store queue ahead of a receipt of the STCX in the higher priority entry; and
ignoring an order of receipt of the operation in the prior entry and the STCX operation in the higher priority entry relative to each when selecting an order for dispatch, wherein said ignoring includes determining when architectural constraints does not prevent selection of the higher priority entry ahead of the prior entry.
5. The method of claim 1 , further comprising dispatching said prior entry ahead of said higher priority entry when said determining step indicates that said architectural constraints prevents selection of the higher priority entry ahead of the prior entry.