DC-DC conversion circuit
View Patent ↗In order to restrict variations of an output voltage of a DC—DC conversion circuit using TFTs, in a boost-type, a second n-ch TFT N 2 and a second p-ch TFT P 2 are newly provided. With regard to the second n-ch TFT N 2 , a gate thereof is connected to a second capacitor C 2 , a source thereof is connected to a first reference voltage source YVDD, and a drain thereof is connected to a first capacitor C 1 . With regard to the second p-ch TFT P 2 , a gate thereof is connected to the second capacitor C 2 , a source thereof is connected to a third capacitor C 3 , and a drain thereof is connected to the first capacitor C 1 . Thus, a voltage at the first capacitor C 1 stops being influenced by the variations of a threshold voltage between a source and drain of a first diode D 1.
1. A DC—DC conversion circuit, comprising:
a first reference voltage source;
a first capacitor in which a first clock signal source is connected to one end;
a second capacitor of which one end is connected to a second clock signal source which outputs an inverted signal of a first clock signal;
a third capacitor for outputting a voltage outputted from the first reference voltage source and boosted;
a first n-ch thin film transistor of which gate is connected to the other end of the first capacitor, source is connected to the first reference voltage source, and drain is connected to the other end of the second capacitor;
a first p-ch thin film transistor of which gate is connected to the other end of the first capacitor, source is connected to the third capacitor, and drain is connected to the other end of the second capacitor;
a first diode connected in a forward direction from the other end of the first capacitor toward the first reference voltage source;
a second n-ch thin film transistor of which gate is connected to the other end of the second capacitor, source is connected to the first reference voltage source, and drain is connected to the other end of the first capacitor; and
a second p-ch thin film transistor of which gate is connected to the other end of the second capacitor, source is connected to the third capacitor, and drain is connected to the other end of the first capacitor.
2. The DC—DC conversion circuit of claim 1 ,
wherein an on/off duty ratio of each of the output signals of the first clock signal source and the second clock signal source is 50%.
3. The DC—DC conversion circuit of claim 1 or 2 , further comprising switching elements connected to an output stage of the first reference voltage source and an input stage of the third capacitor, respectively,
wherein the respective switching elements are turned off during periods from immediately before the first clock signal and the second clock signal are inverted to immediately thereafter.
4. A DC—DC conversion circuit, comprising:
a second reference voltage source;
a fourth capacitor in which a third clock signal source is connected to one end;
a fifth capacitor of which one end is connected to a fourth clock signal source which outputs an inverted signal of a third clock signal;
a sixth capacitor for outputting a voltage outputted from the second reference voltage source and dropped;
a third p-ch thin film transistor of which gate is connected to the other end of the fourth capacitor, source is connected to the second reference voltage source, and drain is connected to the other end of the fifth capacitor;
a third n-ch thin film transistor of which gate is connected to the other end of the fourth capacitor, source is connected to the sixth capacitor, and drain is connected to the other end of the fifth capacitor;
a second diode connected in a forward direction from the other end of the fourth capacitor toward the second reference voltage source;
a fourth p-ch thin film transistor of which gate is connected to the other end of the fifth capacitor, source is connected to the second reference voltage source, and drain is connected to the other end of the fourth capacitor; and
a fourth n-ch thin film transistor of which gate is connected to the other end of the fifth capacitor, source is connected to the sixth capacitor, and drain is connected to the other end of the fourth capacitor.
5. The DC—DC conversion circuit of claim 4 ,
wherein an on/off duty ratio of each of the output signals of the third clock signal source and the fourth clock signal source is 50%.
6. The DC—DC conversion circuit of claim 4 or 5 , further comprising switching elements connected to an output stage of the second reference voltage source and an input stage of the sixth capacitor, respectively,
wherein the respective switching elements are turned off during periods from immediately before the third clock signal and the fourth clock signal are inverted to immediately thereafter.