Trench isolated cross-point memory array
View Patent ↗Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions, isolated from each other by shallow trench isolation. The resistive cross-point memory device is formed by doping lines, which are separated from each other by shallow trench isolation, within a substrate one polarity, and then doping regions of the lines the opposite polarity to form diodes. Bottom electrodes are then formed over the diodes with a layer of resistive memory material overlying the bottom electrodes. Top electrodes may then be added at an angled to form a cross-point array defined by the lines and the top electrodes.
1. A memory structure comprising;
a) a substrate;
b) a plurality of doped lines overlying the substrate and isolated from each other by shallow trench isolation;
c) a plurality of top electrodes overlying the doped bit lines at an angle, whereby a cross-point is formed at each location where a top electrode crosses a doped bit line;
d) a plurality of diodes comprising the doped lines and a doped region of opposite polarity in contact with the doped lines, with each doped region located at a cross-point;
e) a plurality of bottom electrodes overlying the plurality of diodes; and
f) a resistive memory active layer interposed between the plurality of top electrodes and the plurality of bottom electrodes.
2. The memory structure of claim 1 , wherein the doped lines are bit lines.
3. The memory structure of claim 1 , wherein the doped lines are a n-type lines.
4. The memory structure of claim 1 , wherein the doped lines are n-type bit lines and each doped region is a p-type region.
5. The memory structure of claim 1 , wherein the bottom electrodes are platinum, iridium, or ruthenium.
6. The memory structure of claim 1 , wherein the resistive memory active layer is a perovskite material.
7. The memory structure of claim 1 , wherein the resistive memory active layer is a colossal magnetoresistance (CMR) material.
8. The memory structure of claim 1 , wherein the resistive memory active layer is Pr 0.7 Ca 0.3 MnO 3 (PCMO).
9. The memory structure of claim 1 , wherein the resistive memory active layer is Gd 0.7 Ca 0.3 BaCo 2 O 5+5.
10. The memory structure of claim 1 , wherein the resistive memory active layer is continuous, whereby it crosses over multiple cross-points.