Method of fabricating trench isolated cross-point memory array
View Patent ↗Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions, isolated from each other by shallow trench isolation. The resistive cross-point memory device is formed by doping lines, which are separated from each other by shallow trench isolation, within a substrate one polarity, and then doping regions of the lines the opposite polarity to form diodes. Bottom electrodes are then formed over the diodes with a layer of resistive memory material overlying the bottom electrodes. Top electrodes may then be added at an angled to form a cross-point array defined by the lines and the top electrodes.
1. A method of forming a resistive memory array comprising:
a) providing a substrate;
b) implanting ions into the substrate to form a doped-well having a depth;
c) depositing and patterning a polysilicon layer over the doped-well;
d) etching the substrate to form trenches deeper than the depth of the doped-well and define doped lines;
e) filing the trenches with oxide;
f) polishing the oxide until reaching the polysilicon;
g) removing the polysilicon;
h) forming patterned lines perpendicular to the doped lines;
i) depositing a second layer of oxide over the patterned lines;
j) polishing the oxide and patterned lines down to the level of the first layer of oxide;
k) removing the patterned lines;
l) forming spacers by depositing a third layer of oxide and then plasma etching to expose select regions of the doped lines;
m) implanting ions into the exposed regions, whereby a diode is formed;
n) depositing bottom electrodes over the exposed regions and polishing the bottom electrodes level with the first oxide layer;
o) depositing a resistive memory material overlying the bottom electrodes; and
p) forming top electrodes overlying the resistive memory material and aligned with the bottom electrodes.
2. The method of claim 1 , wherein the dopant implanted to form the doped-well is an n-type dopant.
3. The method of claim 1 , wherein the patterned lines are silicon nitride.
4. The method of claim 1 , wherein the patterned lines are polysilicon.
5. The method of claim 1 , further comprising depositing a barrier metal over the exposed regions prior to depositing the bottom electrodes.