Chemical mechanical polish of PCMO thin films for RRAM applications

1. A method of fabricating a CMR layer in a CMOS device using CMP to pattern the CMR layer, comprising:

preparing a silicon substrate, including fabrication of a bottom electrode in the silicon substrate;

depositing a layer of SiN x on the substrate;

patterning and etching the SiN x layer to form a damascene trench over the bottom electrode;

depositing a layer CMR material over the SiN x and in the damascene trench;

removing the CMR material overlying the SiN x layer by CMP, leaving the CMR material in the damascene trench; and

completing the CMOS structure.

2. The method of claim 1 wherein the CMR material is Pr 1-x Ca x MnO 3 .

3. The method of claim 1 wherein said removing the CMR material overlying the SiN x layer by CMP includes providing a silica plus NH 4 OH slurry diluted 1:1 with distilled water.

4. A method of fabricating a Pr 1-x Ca x MnO 3 layer in a CMOS device using CMP to pattern the Pr 1-x Ca x MnO 3 layer, comprising:

preparing a silicon substrate, including fabrication of a bottom electrode in the silicon substrate;

depositing a layer of SiN x on the substrate;

patterning and etching the SiN x layer to form a damascene trench over the bottom electrode;

depositing a layer Pr 1-x Ca x MnO 3 over the SiN x and in the damascene trench;

removing the Pr 1-x Ca x MnO 3 overlying the SiN x layer by CMP, leaving the Pr 1-x Ca X MnO 3 in the damascene trench; and

completing the CMOS structure.

5. The method of claim 4 wherein said removing the CMR material overlying the SiN x layer by CMP includes providing a silica plus NH 4 OH slurry diluted 1:1 with distilled water.