IP Library Granted Patent US 8,090,028
Granted Patent B2
US 8,090,028 · App. 10/972,931 · Granted Jan 3, 2012

Video deblocking memory utilization

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Quick Facts
Patent No.
US 8,090,028
App. No.
10/972,931
Granted
Jan 3, 2012
Kind
B2
Abstract

Methods and systems for processing pixels are disclosed herein. A first portion of a previously processed plurality of pixels may be buffered. A first portion of a plurality of selected pixels within a current macroblock may be filtered utilizing the buffered first portion of previously processed plurality of pixels. A second portion of the previously processed plurality of pixels may be simultaneously buffered while filtering the first portion of the plurality of selected pixels. The previously processed plurality of pixels may comprise pixels within a macroblock pair adjacent to the top of the current macroblock. The current macroblock may comprise a frame coded macroblock and/or a field coded macroblock. A second portion of the plurality of selected pixels within the current macroblock may be filtered utilizing the buffered second portion of the previously processed plurality of pixels.

Claims (49)

1. A method for processing pixels, the method comprising:

performing by one or more processors and/or circuits integrated within a single chip:

buffering in said single chip, a first portion of a plurality of pixels, wherein said plurality of pixels were previously processed by said single chip;

filtering along a first edge adjacent to a current macroblock using a filter in said single chip, a first portion of a plurality of selected pixels within said current macroblock utilizing said buffered first portion of said previously processed plurality of pixels; and

concurrently buffering in said single chip, a second portion of said previously processed plurality of pixels, while filtering said first portion of said plurality of selected pixels within said current macroblock, wherein said concurrently buffered second portion of said previously processed plurality of pixels had previously been filtered along a second edge adjacent to said current macroblock using said filter.

2. The method according to claim 1 , wherein said previously processed plurality of pixels comprise pixels within a macroblock pair adjacent to one of a vertical edge or a horizontal edge of said current macroblock.

3. The method according to claim 1 , wherein said current macroblock comprises one or both of a frame coded macroblock and/or a field coded macroblock.

4. The method according to claim 1 , comprising horizontally or vertically filtering by said filter, a second portion of said plurality of selected pixels within said current macroblock utilizing said buffered second portion of said previously processed plurality of pixels.

5. The method according to claim 4 , comprising rotating in said single chip, said horizontally or vertically filtered second portion of said plurality of selected pixels within said current macroblock.

6. The method according to claim 1 , comprising buffering in said single chip, said filtered first portion of said plurality of selected pixels within said current macroblock.

7. The method according to claim 6 , comprising concurrently horizontally or vertically filtering by said filter, a second portion of said plurality of selected pixels within said current macroblock while buffering said filtered first portion of said plurality of selected pixels within said current macroblock.

8. The method according to claim 7 , comprising storing in said single chip, said buffered first portion of said plurality of selected pixels within said current macroblock.

9. The method according to claim 8 , comprising concurrently buffering in said single chip, said horizontally or vertically filtered second portion of said plurality of selected pixels within said current macroblock while storing in said single chip, said buffered first portion of said plurality of selected pixels within said current macroblock.

10. The method according to claim 1 , comprising determining said first portion of said previously processed plurality of pixels for horizontally or vertically filtering said first portion of said plurality of selected pixels within said current macroblock.

11. The method according to claim 1 , comprising concurrently horizontally or vertically filtering by said filter, a previous portion of a plurality of selected pixels within a previous macroblock while buffering said first portion of said previously processed plurality of pixels.

12. The method according to claim 1 , wherein said first edge and said second edge are perpendicular to each other.

13. The method according to claim 1 , comprising rotating in said single chip, said filtered first portion of said plurality of selected pixels within said current macroblock.

14. A non-transitory computer-readable medium encoded with computer executable instructions for performing a method for processing pixels, comprising:

buffering in a single chip, a first portion of a plurality of pixels, wherein said plurality of pixels were previously processed by said single chip;

filtering along a first edge adjacent to a current macroblock using a filter in said single chip, a first portion of a plurality of selected pixels within said current macroblock utilizing said buffered first portion of said previously processed plurality of pixels; and

concurrently buffering in said single chip, a second portion of said previously processed plurality of pixels, while filtering said first portion of said plurality of selected pixels within said current macroblock, wherein said concurrently buffered second portion of said previously processed plurality of pixels had previously been filtered along a second edge adjacent to said current macroblock using said filter.

15. The non-transitory computer-readable medium according to claim 14 , wherein said previously processed plurality of pixels comprise pixels within a macroblock pair adjacent to one of a vertical edge or a horizontal edge of said current macroblock.

16. The non-transitory computer-readable medium according to claim 14 , wherein said current macroblock comprises one or both of a frame coded macroblock and/or a field coded macroblock.

17. The non-transitory computer-readable medium according to claim 14 , comprising code for horizontally or vertically filtering by said filter, a second portion of said plurality of selected pixels within said current macroblock utilizing said buffered second portion of said previously processed plurality of pixels.

18. The non-transitory computer-readable medium according to claim 17 , comprising code for rotating in said single chip, said horizontally or vertically filtered second portion of said plurality of selected pixels within said current macroblock.

19. The non-transitory computer-readable medium according to claim 14 , comprising code for buffering in said single chip, said filtered first portion of said plurality of selected pixels within said current macroblock.

20. The non-transitory computer-readable medium according to claim 19 , comprising code for concurrently horizontally or vertically filtering by said filter, a second portion of said plurality of selected pixels within said current macroblock while buffering said filtered first portion of said plurality of selected pixels within said current macroblock.

21. The non-transitory computer-readable medium according to claim 20 , comprising code for storing in said single chip, said buffered first portion of said plurality of selected pixels within said current macroblock.

22. The non-transitory computer-readable medium according to claim 21 , comprising code for concurrently buffering in said single chip, said horizontally or vertically filtered second portion of said plurality of selected pixels within said current macroblock while storing said buffered first portion of said plurality of selected pixels within said current macroblock.

23. The non-transitory computer-readable medium according to claim 14 , comprising code for determining said first portion of said previously processed plurality of pixels for horizontally or vertically filtering said first portion of said plurality of selected pixels within said current macroblock.

24. The non-transitory computer-readable medium according to claim 14 , comprising code for concurrently horizontally or vertically filtering by said filter, a previous portion of a plurality of selected pixels within a previous macroblock while buffering in said single chip, said first portion of said previously processed plurality of pixels.

25. The non-transitory computer-readable medium according to claim 14 , wherein said first edge and said second edge are perpendicular to each other.

26. The non-transitory computer-readable medium according to claim 14 , comprising code for rotating in said single chip, said filtered first portion of said plurality of selected pixels within said current macroblock.

27. A system for processing pixels, the system comprising:

at least one processor integrated within a single chip, said at least one processor being operable to buffer in said single chip, a first portion of a plurality of pixels, wherein said plurality of pixels were previously processed by said single chip;

said at least one processor being operable to filter along a first edge adjacent to a current macroblock using a filter in said single chip, a first portion of a plurality of selected pixels within said current macroblock utilizing said buffered first portion of said previously processed plurality of pixels; and

said at least one processor being operable to concurrently buffer in said single chip, a second portion of said previously processed plurality of pixels, while filtering said first portion of said plurality of selected pixels within said current macroblock, wherein said concurrently buffered second portion of said previously processed plurality of pixels had previously been filtered along a second edge adjacent to said current macroblock using said filter.

28. The system according to claim 27 , wherein said previously processed plurality of pixels comprise pixels within a macroblock pair adjacent to one of a vertical edge or a horizontal edge of said current macroblock.

29. The system according to claim 27 , wherein said current macroblock comprises one or both of a frame coded macroblock and/or a field coded macroblock.

30. The system according to claim 27 , wherein said at least one processor is operable to horizontally or vertically filter using said filter, a second portion of said plurality of selected pixels within said current macroblock utilizing said buffered second portion of said previously processed plurality of pixels.

31. The system according to claim 30 , wherein said at least one processor is operable to rotate in said single chip, said horizontally or vertically filtered second portion of said plurality of selected pixels within said current macroblock.

32. The system according to claim 27 , wherein said at least one processor is operable to buffer in said single chip, said filtered first portion of said plurality of selected pixels within said current macroblock.

33. The system according to claim 32 , wherein said at least one processor is operable to concurrently horizontally or vertically filter using said filter, said second portion of said plurality of selected pixels within said current macroblock while buffering in said single chip, said filtered first portion of said plurality of selected pixels within said current macroblock.

34. The system according to claim 33 , wherein said at least one processor is operable to store in said single chip, said buffered first portion of said plurality of selected pixels within said current macroblock.

35. The system according to claim 34 , wherein said at least one processor is operable to concurrently buffer in said single chip, said horizontally or vertically filtered second portion of said plurality of selected pixels within said current macroblock while storing in said single chip, said buffered first portion of said plurality of selected pixels within said current macroblock.

36. The system according to claim 27 , wherein said at least one processor is operable to determine said first portion of said previously processed plurality of pixels for horizontally or vertically filtering said first portion of said plurality of selected pixels within said current macroblock.

37. The system according to claim 27 , wherein said at least one processor is operable to concurrently horizontally or vertically filter using said filter, a previous portion of a plurality of selected pixels within a previous macroblock while buffering in said single chip, said first portion of said previously processed plurality of pixels.

38. The system according to claim 27 , wherein said first edge and said second edge are perpendicular to each other.

39. The system according to claim 27 , wherein said at least one processor is operable to rotate in said single chip, said filtered first portion of said plurality of selected pixels within said current macroblock.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE PROPERTY NUMBERS PREVIOUSLY RECORDED AT REEL: 47630 FRAME: 344. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 21, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0267 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 9/5/2018 PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0687. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0344 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0687 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 25, 2009
From: BROADCOM ADVANCED COMPRESSION GROUP, LLC
To: BROADCOM CORPORATION
Reel/Frame 022299/0916 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 24, 2005
From: HELLMAN, TIMOTHY
To: BROADCOM ADVANCED COMPRESSION GROUP LLC
Reel/Frame 015617/0755 →