Rate-7/8 maximum transition run code encoding and decoding method and apparatus

1. A rate-7/8 maximum transition run (MTR) code encoding method comprising:

generating a rate-7/8 MTR code for inputting 7-bit data and outputting a predetermined 8-bit codeword;

checking whether codewords satisfy a predetermined constraint condition by connecting the predetermined 8-bit codeword and a subsequent 8-bit codeword; and

converting the codewords if the codewords violate the constraint condition and not converting the codewords if the codewords do not violate the constraint condition;

wherein the rate-7/8 MTR code comprises:

98 codewords remaining after excluding ‘00000000’, ‘00000001’, ‘00100000’, ‘01000000’, ‘01100000’, ‘10000000’, and ‘10100000’ from 105 codewords each including no more than one ‘1’ at the first two bits thereof and no more than one ‘1’ at the last two bits thereof so that an MTR constraint condition (j=2) indicating allowable consecutive data transitions is satisfied when codewords are consecutively input, among 256 8-bit codewords; and

codewords obtained by excluding the codeword ‘11010000’ and 13 codewords beginning with ‘1100’ from 44 codewords beginning with ‘110’or ending with ‘011’.

2. The method of claim 1 , wherein the checking of whether the codewords satisfy the predetermined constraint condition comprises:

when a codeword is connected to one of the 128 codewords and c(k) represents a current codeword to be checked to determine whether or not the constraint condition is violated and c(k+1) represents a subsequent codeword, determining whether the last 2 bits (x 1 , x 0 ) of the current codeword and the first 4 bits (y 7 , y 6 , y 5 , y 4 ) of the subsequent codeword violate the constraint condition, and

the converting of the codewords comprises:

when z 0 indicates a parameter for determining whether the number of consecutive ‘0’s is equal to or less than 7 and z 1 indicates a parameter for determining whether codewords satisfy a constraint condition (j=3), calculating z 0 and z 1 using z 0 =x 1 +x 0 +y 7 +y 6 +y 5 +y 4 , z 1 =x 1 ·x 0 ·y 7 ·y 6 ·y 4 (here, +indicates a modular-2 add operation);

when z 0 =0, converting x 0 , y 7 , and y 6 to 1 to satisfy k=7; and

when z 1 =1, converting x 0 and y 4 to 0 so that j does not exceed 3.

3. A rate-7/8 maximum transition run (MTR) code encoding apparatus comprising:

a 7/8 encoder generating a rate-7/8 MTR code for inputting 7-bit data and outputting a predetermined 8-bit codeword; and

an MTR violation checking and converting unit checking whether codewords satisfy a predetermined constraint condition by connecting the predetermined 8-bit codeword and a subsequent 8-bit codeword, converting specific bits of the codewords if the codewords violate the constraint condition, and not converting the codewords if the codewords do not violate the constraint condition;

wherein the rate-7/8 MTR code comprises:

98 codewords remaining after excluding ‘00000000’, ‘00000001’, ‘00100000’, ‘01000000’, ‘01100000’, ‘10000000’, and ‘10100000’ from 105 codewords each including no more than one ‘1’ at the first two bits thereof and no more than one ‘1’ at the last two bits thereof so that an MTR constraint condition (j=2) indicating allowable consecutive data transitions is satisfied when codewords are consecutively input, among 256 8-bit codewords; and

30 codewords obtained by excluding the codeword ‘11010000’ and 13 codewords beginning with ‘1100’ from 44 codewords beginning with ‘110’or ending with ‘011’, and wherein

when a codeword is connected to one of the 128 codewords and c(k) represents a current codeword to be checked to determine whether or not the constraint condition is violated and c(k+1) represents a subsequent codeword, checking of the MTR constraint condition in the MTR violation checking and converting unit is achieved by determining whether the last 2 bits (x 1 , x 0 ) of the current codeword and the first 4 bits (y 7 , y 6 , y 5 , y 4 ) of the subsequent codeword violate the MTR constraint condition; and

when z 0 indicates a parameter for determining whether the number of consecutive ‘0’s is equal to or less than 7 and z 1 indicates a parameter for determining whether codewords satisfy a constraint condition (j=3), the codeword conversion in the MTR violation checking and converting unit is achieved by calculating z 0 and z 1 using z 0 =x 1 +x 0 +y 7 +y 6 +y 5 +y 4 , z 1 =x 1 ·x 0 ·y 7 ·y 6 ·y 4 (here, +indicates a modular-2 add operation), converting x 0 , y 7 , and y 6 to 1 to satisfy k=7 when z 0 =0, and converting x 0 and y 4 to 0 so that j does not exceed 3 when z 1 =1.

4. The apparatus of claim 3 , further comprising:

a parallel-to-serial converter converting parallel codewords of the MTR violation checking and converting unit to serial data; and

a precoder changing a signal level of the serial data in order to record the serial data in a channel.

5. A rate-7/8 maximum transition run (MTR) code decoding method comprising:

when c(k) represents a currently input 8-bit codeword and c(k+1) represents a subsequently input 8-bit codeword, checking whether the codewords satisfy a predetermined MTR constraint condition by connecting c(k) and c(k+1);

if the codewords violate the MTR constraint condition, converting the codewords, and if the codewords do not violate the MTR constraint condition, not converting the codewords; and

decoding each converted 8-bit codeword into 7-bit data using a predetermined MTR code;

wherein the rate-7/8 MTR code comprises:

98 codewords remaining after excluding ‘00000000’, ‘00000001’, ‘00100000’, ‘01000000’, ‘01100000’, ‘10000000’, and ‘10100000’ from 105 codewords each including no more than one ‘1’ at the first two bits thereof and no more than one ‘1’ at the last two bits thereof so that an MTR constraint condition (j=2) indicating allowable consecutive data transitions is satisfied when codewords are consecutively input, among 256 8-bit codewords; and

30 codewords obtained by excluding the codeword ‘11010000’ and 13 codewords beginning with ‘1100’ from 44 codewords beginning with ‘110’or ending with ‘011’.

6. The method of claim 5 , wherein the checking of whether the codewords satisfy the predetermined MTR constraint condition comprises:

when a codeword is connected to one of the 128 codewords and c(k) represents a current codeword to be checked to determine whether or not the constraint condition is violated and c(k+1) represents a subsequent codeword, determining whether the last 2 bits (x 1 , x 0 ) of the current codeword and the first 4 bits (y 7 , y 6 , y 5 , y 4 ) of the subsequent codeword violate the MTR constraint condition; and

the converting or not converting the codewords comprises:

when z 0 indicates a parameter for determining whether the number of consecutive ‘0’s is equal to or less than 7 and z 1 indicates a parameter for determining whether codewords satisfy a constraint condition (j=3), calculating z 0 and z 1 using z 0 =x 0 ·y 7 ·y 6 ·{overscore (y 4 )}, z 1 =x 1 ·y 7 ·y 6 ·{overscore (y 4 )};

when z 0 =0, converting x 0 , y 7 , and y 6 to 0 to satisfy k=7; and

when z 1 =1, converting x 0 and y 4 to 1 so that j does not exceed 3.

7. The method of claim 5 , wherein the currently input codeword is equalized by an output of a reproducing channel, and an equalized result is decoded by inputting the equalized result to a Viterbi decoder having a trellis obtained by combining a j=2 trellis and a j=3 trellis, and

the combined trellis is a modified j=3 trellis allowing 3 consecutive bits from a beginning bit of a boundary between connected codewords to satisfy a j=3 condition.

8. The method of claim 6 , wherein the currently input codeword is equalized by an output of a reproducing channel, and an equalized result is decoded by inputting the equalized result to a Viterbi decoder having a trellis obtained by combining a j=2 trellis and a j=3 trellis, and

the combined trellis is a modified j=3 trellis allowing 3 consecutive bits from a beginning bit of a boundary between connected codewords to satisfy a j=3 condition.

9. The method of claim 7 , wherein the fourth bit (x 4 ) through the LSB (x 0 ) of the current codeword are decoded using the j=2 trellis, and

to apply the j=3 trellis to the first two bits y 7 and y 6 of the subsequent codeword, a trellis corresponding to y 7 is obtained by calculating the following additional branch metrics in the j=2 trellis

BM (α k =+1|α k−1 =−1, α k−2 =+1, α k-3 =−1, α k−4 =−1)

BM (α k −+1|α k−1 =+1, α k−2 =−1, α k-3 =+1, α k−4 =+1)

a trellis corresponding to y 6 is obtained by calculating the following additional branch metrics in the j=2 trellis

BM (α k =+1|α k−1 =−1, α k−2 =+1, α k−3 =−1, α k−4 =−1)

BM (α k =+1|α k−1 =+1, α k−2 =−1, α k−3 =+1, α k−4 =−1)

BM (α k =−1|α k−1 =−1, α k−2 =+1, α k−3 =−1, α k−4 =+1)

BM (α k =−1|α k−1 =+1, α k−2 =−1, α k−3 =+1, α k−4 =+1)

and a trellis corresponding to y 5 is obtained by calculating the following additional branch metrics in the j=2 trellis

BM (α k =+1|α k−1 =+1, α k−2 =−1, α k−3 =+1, α k−4 =−1)

BM (α k =+1|α k−1 =−1, α k−2 =+1, α k−3 =−1, α k−4 =+1).

10. A rate-7/8 maximum transition run (MTR) code decoding apparatus comprising:

an MTR violation checking and converting unit, when c(k) represents a currently input 8-bit codeword and c(k+1) represents a subsequently input 8-bit codeword, checking whether the codewords satisfy a predetermined MTR constraint condition by connecting c(k) and c(k+1), and if the codewords violate the MTR constraint condition, converting the codewords, and if the codewords do not violate the MTR constraint condition, not converting the codewords; and

a 7/8 decoder decoding each 8-bit codeword output from the MTR violation checking and converting unit into 7-bit data using a predetermined MTR code;

wherein the rate-7/8 MTR code comprises:

98 codewords remaining after excluding ‘00000000’, ‘00000001’, ‘00100000’, ‘01000000’, ‘01100000’, ‘10000000’, and ‘10100000’ from 105 codewords each including no more than one ‘1’ at the first two bits thereof and no more than one ‘1’ at the last two bits thereof so that an MTR constraint condition (j=2) indicating allowable consecutive data transitions is satisfied when codewords are consecutively input, among 256 8-bit codewords; and

30 codewords obtained by excluding the codeword ‘11010000’ and 13 codewords beginning with ‘1100’ from 44 codewords beginning with ‘110’or ending with ‘011’.

11. The apparatus of claim 10 , wherein, when a codeword is connected to one of the 128 codewords and c(k) represents a current codeword to be checked to determine whether or not the constraint condition is violated and c(k+1) represents a subsequent codeword, checking of the MTR constraint condition in the MTR violation checking and converting unit is achieved by determining whether the last 2 bits (x 1 , x 0 ) of c(k) and the first 4 bits (y 7 , y 6 , y 5 , y 4 ) of c(k+1) violate the MTR constraint condition, and

when z 0 indicates a parameter for determining whether the number of consecutive ‘0’s is equal to or less than 7 and z 1 indicates a parameter for determining whether codewords satisfy a constraint condition (j=3), the codeword conversion in the MTR violation checking and converting unit is achieved by calculating z 0 and z 1 using z 0 =x 0 ·y 7 ·y 6 ·{overscore (y 4 )}, z 1 =x 1 ·y 7 ·y 6 ·{overscore (y 4 )}, converting x 0 , y 7 , and y 6 to 0 to satisfy k=7 when z 0 =0, and converting x 0 and y 4 to 1 so that j does not exceed 3 when z 1 =1.

12. The apparatus of claim 10 , further comprising:

a fourth order partial response equalizer equalizing data received through a channel to compensate a reproducing characteristic of the channel with respect to a currently input 8-bit codeword and a subsequent 8-bit codeword;

a Viterbi decoder including a trellis obtained by combining a j=2 trellis and a j=3 trellis, which is a modified j=3 trellis allowing consecutive 3 bits from a beginning bit of a boundary between connected codewords to satisfy a j=3 condition, and Viterbi decoding the equalized result using the combined trellis; and

a serial-to-parallel converter converting serial data of the Viterbi decoder to parallel data.

13. The apparatus of claim 1 further comprising:

a fourth order partial response equalizer equalizing data received through a channel to compensate a reproducing characteristic of the channel with respect to a currently input 8-bit codeword and a subsequent 8-bit codeword;

a Viterbi decoder including a trellis obtained by combining a j=2 trellis and a j=3 trellis, which is a modified j=3 trellis allowing consecutive 3 bits from a beginning bit of a boundary between connected codewords to satisfy a j=3 condition, and Viterbi decoding the equalized result using the combined trellis; and

a serial-to-parallel converter converting serial data of the Viterbi decoder to parallel data.

14. A computer readable medium having recorded thereon a computer readable program for performing a rate-7/8 maximum transition run (MTR) code encoding method comprising:

generating a rate-7/8 MTR code for inputting 7-bit data and outputting a predetermined 8-bit codeword;

checking whether codewords satisfy a predetermined constraint condition by connecting the predetermined 8-bit codeword and a subsequent 8-bit codeword; and

converting the codewords if the codewords violate the constraint condition and not converting the codewords if the codewords do not violate the constraint condition;

wherein the rate-7/8 MTR code comprises:

98 codewords remaining after excluding ‘00000000’, ‘00000001’, ‘00100000’, ‘01000000’, ‘01100000’, ‘10000000’, and ‘10100000’ from 105 codewords each including no more than one ‘1’ at the first two bits thereof and no more than one ‘1’ at the last two bits thereof so that an MTR constraint condition (j=2) indicating allowable consecutive data transitions is satisfied when codewords are consecutively input, among 256 8-bit codewords; and

30 codewords obtained by excluding the codeword ‘11010000’ and 13 beginning with ‘1100’ from 44 codewords beginning with ‘110’or ‘011’.