IP Library Granted Patent US 7,276,391
Granted Patent B2
US 7,276,391 · App. 10/974,226 · Granted Oct 2, 2007

Manufacture of a semiconductor device

Assignee: Sharp Kabushiki Kaisha
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Quick Facts
Patent No.
US 7,276,391
App. No.
10/974,226
Granted
Oct 2, 2007
Kind
B2
Abstract

A method of fabricating the active region of a semiconductor light-emitting device, in which the active region comprises a plurality of barrier layers ( 11,13,15,17 ) with each pair of barrier layers being separated by a quantum well layer ( 12,14,16 ), comprises annealing each barrier layer ( 11,13,15,17 ) separately. Each barrier layer ( 11,13,15,17 ) is annealed once it has been grown, and before a layer is grown over the barrier layer. A device grown by the method of the invention has a significantly higher optical power output than a device made by a convention fabrication process having a single annealing step.

Claims (24)

1. A method of fabricating the active region of a semiconductor light-emitting device in a nitride material system, the method comprising, in order, the steps of:

a) growing a first barrier layer;

b) annealing the first barrier layer at a temperature greater than the growth temperature of step (a);

c) growing a first quantum well layer over the first barrier layer;

d) growing a second barrier layer over the first quantum well layer; and

e) annealing the second barrier layer at a temperature greater than the growth temperature of step (d).

2. A method as claimed in claim 1 and comprising the further steps of:

f) growing a second quantum well layer over the second barrier layer,

g) growing a third barrier layer over the second quantum well layer, and

h) annealing the third barrier layer at a temperature greater than the growth temperature of step (g).

3. A method as claimed in claim 1 wherein each annealing step comprises annealing the respective barrier layer at a temperature at least 50° C. greater than the growth temperature of the layer.

4. A method as claimed in claim 2 wherein each annealing step comprises annealing the respective barrier layer at a temperature at least 50° C. greater than the growth temperature of the layer.

5. A method as claimed in claim 1 wherein each barrier layer is a layer of Al x Ga 1−x N (0≦x≦0.4), In x Ga 1−x N (0≦x≦0.05) or AlGaInN.

6. A method as claimed in claim 1 wherein the growth temperature of each barrier layer is at least 500° C.

7. A method as claimed in claim 1 wherein the growth temperature of each barrier layer is less than 1050° C.

8. A method as claimed in claim 1 wherein the annealing temperature of each barrier layer is at least 700° C.

9. A method as claimed in claim 1 wherein the annealing temperature of each barrier layer is at least 850° C.

10. A method as claimed in claim 1 wherein the annealing temperature of each barrier layer is less than 1100° C.

11. A method as claimed in claim 1 wherein the annealing temperature of each barrier layer is less than 1000° C.

12. A method as claimed in claim 1 wherein the growth temperature of the quantum well layer is at least 500° C.

13. A method as claimed in claim 1 wherein the growth temperature of the quantum well layer is less than 850° C.

14. A method as claimed in claim 1 wherein the quantum well layer comprises a layer of In x Ga 1−x N (0≦x≦0.3), Al x Ga 1−x N (0≦x≦0.1) or AlGaInN.

15. A method as claimed in claim 1 wherein the device is a light-emitting diode.

16. A method as claimed in claim 1 wherein the device is a laser device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 28, 2005
From: HOOPER, STEWART; BOUSQUET, VALERIE; JOHNSON, KATHERINE L.; HEFFERNAN, JONATHAN
To: SHARP KABUSHIKI KAISHA
Reel/Frame 015825/0841 →
Priority Claims (1)
GB 0325099.0 · Oct 28, 2003 · national
Continuity (1)
Related Publication 20050170537A1 · Aug 4, 2005