IP Library Granted Patent US 7,327,080
Granted Patent B2
US 7,327,080 · App. 10/974,311 · Granted Feb 5, 2008

Hybrid active matrix thin-film transistor display

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Quick Facts
Patent No.
US 7,327,080
App. No.
10/974,311
Granted
Feb 5, 2008
Kind
B2
Abstract

A field emission display comprises an anode comprising a matrix of pixels and a cathode comprising an insulating layer defining a plurality of wells having a conductor therein. A first conductive layer forms a plurality of conductive pads, each of the conductive pads corresponding to one of the wells. A plurality of nanostructures are electrically coupled to the conductive pads. A second conductive layer is formed over the insulating layer and provides a plurality of gate electrodes. When a potential between the conductive pads and gate electrodes exceeds a threshold voltage, the nanostructures emit electrons that impinge on the pixels.

Claims (58)

1. A field emission display comprising:

an anode comprising a matrix of pixels; and,

a cathode comprising:

an insulating layer defining a plurality of wells having a conductor therein;

a first conductive layer forming a plurality of conductive pads, each of said conductive pads corresponding to one of said wells;

a plurality of nanostructures electrically coupled to said conductive pads;

a second conductive layer formed over said insulating layer and providing a plurality of gate electrodes;

driver circuitry comprising:

first and second n-channel transistors, the first n-channel transistor having gate and drain terminals coupled to a given voltage, and a source terminal coupled to a drain terminal of the second n-channel transistor; and, the second n-channel transistor has a gate terminal for providing a column driver data signal and a source terminal coupled to another given voltage; and

a third n-channel transistor having a drain terminal coupled to the source terminal of the first n-channel transistor and the drain terminal of the second n-channel transistor and the input to the pixel circuit stage; wherein a gate terminal of the third n-channel transistor is selectively provided with a horizontal blanking signal and a source terminal of the third n-channel transistor is substantially grounded;

wherein, when a potential between said conductive pads and gate electrodes exceeds a threshold voltage, said nanostructures emit electrons that impinge said pixels.

2. The display of claim 1 , wherein at least one of said first and second conductive layers comprise nickel.

3. The display of claim 1 , wherein at least one of said first and second conductive layers comprise chromium.

4. The display of claim 1 , wherein said nanostructures comprise carbon nanotubes.

5. The display of claim 4 , wherein said carbon nanotubes are arranged in a regular array upon said pads.

6. The display of claim 1 , further comprising a plurality of spacers interposed between said anode and cathode.

7. The display of claim 6 , wherein said spacers comprise an insulator.

8. The display of claim 6 , wherein said spacers comprise a photoresist.

9. A field emission display comprising:

an anode comprising a matrix of pixels, wherein each pixel has associated therewith driver circuitry comprising first, second and third transistors, wherein:

the first transistor has gate and drain terminals coupled to a given voltage, and a source terminal coupled to a drain terminal of the second transistor;

the second transistor has a gate terminal for providing a column driver data signal and a source terminal coupled to another given voltage; and,

the third transistor has a gate terminal for providing row driver data signal and a drain terminal coupled to the source terminal of the first transistor and the drain terminal of the second transistor; and

a cathode comprising:

an insulating layer defining a plurality of wells having a conductor therein;

a first conductive layer forming a plurality of conductive pads, each of said conductive pads corresponding to one of said wells;

a plurality of structures electrically coupled to said conductive pads; and

a second conductive layer formed over said insulating layer and providing a plurality of gate electrodes;

wherein, when a potential between said conductive pads and gate electrodes exceeds a threshold voltage, said structures emit electrons that impinge said pixels.

10. A field emission display comprising:

an anode comprising a matrix of pixels; and,

a cathode comprising;

an insulating layer defining a plurality of wells having a conductor therein; a first conductive layer forming a plurality of conductive pads, each of said conductive pads corresponding to one of said wells;

a plurality of nanostructures electrically coupled to said conductive pads;

a second conductive layer formed over said insulating layer and providing a plurality of gate electrodes;

driver circuitry comprising:

a p-channel transistor having a source terminal coupled to a given voltage, a gate terminal coupled to another given voltage;

a first n-channel transistor having a drain terminal coupled to a drain terminal of the p-channel transistor, a gate terminal having a column driver data signal provided thereon, and a source terminal having a third given voltage provided thereon;

a second n-channel transistor having a drain terminal coupled to the drain terminal of the p-channel transistor and the drain terminal of first n-channel transistor, a gate terminal selectively provided with a horizontal blanking signal, and a substantially grounded source terminal.

11. A field emission display comprising:

an anode comprising a matrix of pixels; and,

a cathode comprising:

an insulating layer defining a plurality of wells having a conductor therein; a first conductive layer forming a plurality of conductive pads, each of said conductive pads corresponding to one of said wells;

a plurality of structures electrically coupled to said conductive pads;

a second conductive layer formed over said insulating layer and providing a plurality of gate electrodes;

driver circuitry comprising:

first and second n-channel transistors, the first n-channel transistor having gate and drain terminals coupled to a given voltage, and a source terminal coupled to a drain terminal of the second n-channel transistor; and, the second n-channel transistor has a gate terminal for providing a column driver data signal and a source terminal coupled to a given voltage; and

a third n-channel transistor having a drain terminal coupled to the source terminal of the first n-channel transistor and the drain terminal of the second n-channel transistor and the input to the pixel circuit stage; wherein a gate terminal of the third n-channel transistor is selectively provided with a horizontal blanking signal and a source terminal of the third n-channel transistor is substantially grounded;

wherein, when a potential between said conductive pads and gate electrodes exceeds a threshold voltage, said stuctures emit electrons that impinge said pixels.

12. A field emission display comprising:

an anode comprising a matrix of pixels; and,

a cathode comprising:

an insulating layer defining a plurality of wells having a conductor therein; a first conductive layer forming a plurality of conductive pads, each of said conductive pads corresponding to one of said wells;

a plurality of structures electrically coupled to said conductive pads;

a second conductive layer formed over said insulating layer and providing a plurality of gate electrodes;

driver circuitry comprising:

a p-channel transistor having a source terminal coupled to a given voltage, a gate terminal coupled to another given voltage;

a first n-channel transistor having a drain terminal coupled to a drain terminal of the p-channel transistor, a gate terminal having a column driver data signal provided thereon, and a source terminal having another given voltage provided thereon; a second n-channel transistor having a drain terminal coupled to the drain terminal of the p-channel transistor and the drain terminal of first n-channel transistor, a gate terminal selectively provided with a horizontal blanking signal, and a substantially grounded source terminal.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 17, 2015
From: ITUS CORPORATION
To: ITUS CORPORATION
Reel/Frame 035849/0190 →
CHANGE OF NAME Recorded Oct 29, 2014
From: COPYTELE, INC.
To: ITUS CORPORATION
Reel/Frame 034095/0469 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2004
From: DISANTO, FRANK J.; KRUSOS, DENIS A.; SHOKHOR, SEGEY L.; KASTALSKY, ALEXANDER; CAMPISI, ANTHONY J.
To: COPYTELE, INC.
Reel/Frame 016091/0724 →
Continuity (4)
Continuation In Part 1078258000 · Feb 19, 2004
Continuation In Part 1076303000 · Jan 22, 2004
Continuation In Part 1010247200 · Mar 20, 2002
Related Publication 20050168131A1 · Aug 4, 2005