Method and apparatus for converting PWM signal to analog output voltage

1. A circuit for converting a duty cycle of a pulse width modulated signal to an analog value comprising:

a clock signal generator for generating a clock signal;

a window generation circuit for generating a window signal synchronized with the pulse width modulated signal having a window having a window start and a window termination;

a counter drive circuit receiving the clock signal, the pulse width modulated signal and the window signal and producing a counter input signal;

a counter circuit for counting pulses of the counter input signal and providing a counter output;

a reset circuit for resetting the counter at the termination of the window; and

a digital to analog converter for converting the counter output at the termination of the window to the analog value.

2. The circuit of claim 1 , further comprising a circuit for synchronizing the pulse width modulated signal to the clock signal.

3. The circuit of claim 2 , further comprising a latch circuit for latching the counter output and providing a latched counter output to the digital to analog converter.

4. The circuit of claim 3 , wherein the reset circuit comprises a circuit for providing a reset signal to the counter circuit to reset the counter circuit.

5. The circuit of claim 4 , further comprising a circuit for setting the latch circuit at the termination of the window.

6. The circuit of claim 3 , further comprising a delay circuit for resetting the counter circuit after latching of the counter output by the latch circuit.

7. The circuit of claim 1 , wherein the window is a fixed time duration from start to termination for a specified clock signal frequency.

8. The circuit of claim 7 , wherein the fixed time duration of the window varies inversely as the clock signal frequency.

9. The circuit of claim 1 , wherein the counter circuit counts clock pulses of the clock signal only during the window of the window signal and only during a duty cycle portion of the pulse width modulated signal.

10. The circuit of claim 1 , wherein the counter output is independent of the frequency of the pulse width modulated signal and the clock signal.

11. A method for converting a duty cycle of a pulse width modulated signal to an analog value comprising:

generating a clock signal;

generating a window signal synchronized with the pulse width modulated signal having a window having a window start and a window termination;

receiving the clock signal, the pulse width modulated signal and the window signal and producing a counter input signal;

counting pulses of the counter input signal and providing a counter output;

resetting the step of counting at the termination of the window; and

converting the counter output at the termination of the window to the analog value.

12. The method of claim 11 , further comprising synchronizing the pulse width modulated signal to the clock signal.

13. The method of claim 11 , further comprising latching the counter output and providing a latched counter output for conversion to the analog value.

14. The method of claim 13 , further comprising providing a reset signal to reset the step of counting.

15. The method of claim 14 , further comprising latching the counter output at the termination of the window.

16. The method of claim 13 , further comprising resetting the step of counting after latching of the counter output.

17. The method of claim 11 , wherein the window is a fixed time duration for a specified clock signal frequency.

18. The method of claim 17 , wherein the fixed time duration of the window varies inversely as the clock signal frequency.

19. The method of claim 11 , wherein the step of counting pulses of the counter input signal comprises counting clock pulses of the clock signal only during the window of the window signal and only during a duty cycle of the pulsed width modulated signal.

20. The method of claim 11 , wherein the counter output is independent of the frequency of the pulse width modulated signal and the clock signal.