Method and system for providing a power-on reset pulse
View Patent ↗Provided are a method and system for providing a power-on reset pulse. The system includes a level detector configured to receive an input signal and produce, at least indirectly, a reset signal when the input signal reaches a predetermined level. The system also includes a counter having counting characteristics and configured to receive the reset signal and a clock signal. The counter produces a delayed signal in accordance with the counting characteristics, the clock signal, and the received reset signal.
1. An apparatus, comprising:
a level detector configured to (i) receive an input signal and (ii) produce a threshold signal when the input signal reaches a predetermined level; and
a delay circuit configured to receive the input signal and produce an output signal in accordance with a predetermined delay factor, the output signal being provided as an input to the level detector; and
a counter having counting characteristics and configured to (i) receive an input reset signal and a clock signal and (ii) produce a delayed signal in accordance with the counting characteristics, the clock signal, and the received input reset signal;
wherein the delayed signal forms an output reset pulse.
2. The apparatus of claims 1 , wherein the apparatus is a power-on reset circuit.
3. The apparatus of claim 1 , wherein the level detector and the counter are formed on a single integrated circuit (IC).
4. The apparatus of claim 3 , further comprising a clock generator to produce the clock signal.
5. The apparatus of claim 4 , wherein the clock generator is formed on the IC.
6. The apparatus of claim 3 , wherein the delay circuit is formed on the IC.
7. The apparatus of claim 1 , wherein the threshold signal is logically combined with the output signal to produce the input reset signal.
8. The apparatus of claim 4 , wherein the delayed signal is provided as an input to the clock generator and the delay circuit.
9. A method for producing an output reset pulse, comprising:
detecting a level of a received input signal;
producing a threshold signal when the input signal reaches a predetermined level; and
producing an output signal in accordance with a predetermined delay factor, the detecting being based upon the output signal; and
counting in accordance with a reset signal and a received clock signal, the counting producing a delayed signal, the delayed signal forming the output reset pulse.
10. The method of claim 9 , further comprising logically combining the threshold signal and the output signal to produce the input reset signal.
11. The method of claim 10 , wherein the logically combining includes a logical NAND operation.