IP Library Granted Patent US 7,235,867
Granted Patent B1
US 7,235,867 · App. 10/976,876 · Granted Jun 26, 2007

Semiconductor device with electrically biased die edge seal

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Quick Facts
Patent No.
US 7,235,867
App. No.
10/976,876
Granted
Jun 26, 2007
Kind
B1
Abstract

A die seal arrangement and method for making the same negatively biases the die edge seal of a die by connecting the die edge seal to a source of negative electrical potential, with respect to electrical ground. The die edge seal, made of copper, for example, has its oxidation reaction potential shifted to a region which is energetically unfavorable. This significantly retards or eliminates oxidation of the copper die edge seal at circuit operation temperature, thereby maintain the integrity and functionality of the die edge seal to protect active circuitry on the die, even when the die edge seal is exposed to moisture and air.

Claims (17)

1. A die edge seal arrangement for a semiconductor device, comprising:

a metallic edge seal surrounding active circuitry on a die; and

a source of negative electrical potential with respect to electrical ground coupled to the edge seal to negatively bias the edge seal.

2. The arrangement of claim 1 , wherein the edge seal is made of copper.

3. The arrangement of claim 2 , wherein the source of negative electrical potential is a negative supply rail of the semiconductor device.

4. The arrangement of claim 2 , wherein the source of negative electrical potential is a battery.

5. The arrangement of claim 4 , further comprising a printed circuit board (PCB) on which the die is mounted, the battery being mounted on the PCB.

6. The arrangement of claim 1 , wherein the edge seal is made of a copper alloy.

7. A semiconductor device arrangement comprising:

a die having a die edge seal; and

means for preventing oxidation of the die edge seal.

8. A semiconductor device arrangement comprising:

a die having a die edge seal; and

means for preventing oxidation of the die edge seal, wherein the means for preventing oxidation includes means for negatively biasing the die edge seal.

9. The arrangement of claim 8 , wherein the means for negatively biasing the die edge seal include a battery connected to the die edge seal.

10. The arrangement of claim 8 , wherein the means for negatively biasing the die edge seal include a negative supply rail on the die, the negative supply rail being electrically connected to the die.

11. The arrangement of claim 8 , wherein the die edge seal is made of copper.