Automatically synchronizing timed circuits on I/O Devices

1. A computer-implemented method for automatic synchronization of I/O devices, comprising:

creating a graphical program in response to user input, wherein the graphical program specifies timing configuration and operation of a plurality of timed circuits comprised on one or more I/O devices; and

executing the graphical program to perform an I/O operation using the one or more I/O devices, wherein said executing comprises invoking software to perform:

analyzing the plurality of timed circuits to determine timing and triggering information for synchronous operation of the plurality of timed circuits, wherein said analyzing comprises:

determining the number and types of timing signals for each of the plurality of timed circuits;

determining sharing of the timing signals in order to synchronize the timed circuits;

determining sources of timing signals for each of the plurality of timed circuits;

determining timing signal routes from each of the sources to the plurality of timed circuits; and

determining a starting order of the plurality of timed circuits;

configuring the timed circuits in accordance with the timing and triggering information; and

operating the configured plurality of timed circuits to perform the I/O operation in a synchronous manner, wherein said operating the plurality of timed circuits comprises:

initiating operation of each of the plurality of timed circuits in accordance with the determined starting order.

2. The computer-implemented method of claim 1 , wherein said analyzing the plurality of timed circuits comprises:

determining the plurality of timed circuits, wherein each of the plurality of timed circuits comprises one of:

an input circuit comprising one or more input channels, wherein the input circuit is operable to read data from the one or more input channels and provide the data to the graphical program; and

an output circuit comprising one or more output channels, wherein the output circuit is operable to receive data from the graphical program and write the data to the one or more output channels.

3. The computer-implemented method of claim 1 ,

wherein said analyzing the plurality of timed circuits comprises:

determining a stopping order of the plurality of timed circuits; and

wherein said operating the plurality of timed circuits comprises:

terminating operation of each of the plurality of timed circuits in accordance with the determined stopping order.

4. The computer-implemented method of claim 1 ,

wherein the plurality of timed circuits comprises two or more instances of a timing signal, and wherein the method further comprises:

receiving input requesting export of a timing signal from the plurality of timed circuits;

wherein said analyzing the plurality of timed circuits comprises:

determining a source of a timing signal for export by selecting one of the two or more instances of the timing signal as the exported timing signal; and

wherein said operating the plurality of timed circuits comprises:

exporting the selected one of the two or more instances of the timing signal.

5. The computer-implemented method of claim 1 , further comprising:

receiving user input specifying property settings for the plurality of timed circuits;

wherein said analyzing the plurality of timed circuits comprises:

for each specified property setting, determining if the property setting can be applied directly to each of the plurality of timed circuits, or if the property setting must be modified for application to one or more of the plurality of timed circuits; and

wherein said configuring the timed circuits comprises:

for each specified property setting,

if the property setting can be applied directly to each of the plurality of timed circuits, applying the specified property settings to each of the plurality of timed circuits; and

if the property setting must be modified for application to one or more of the plurality of timed circuits, modifying the property setting and applying the modified setting to the one or more of the plurality of timed circuits.

6. The computer-implemented method of claim 1 , wherein said executing the graphical program comprises querying a value of a property, comprising invoking the software to perform:

determining one or more of the plurality of timed circuits to query;

querying the determined one or more timed circuits for the value of the property;

if two or more timed circuits are queried, determining, whether to return a minimum, maximum, sum, or average of a plurality of values queried; and

returning the value of the property to the graphical program.

7. The computer-implemented method of claim 1 , wherein the plurality of timed circuits are comprised on a plurality of I/O devices.

8. The computer-implemented method of claim 1 , wherein the plurality of timed circuits are comprised on a single I/O device.

9. The computer-implemented method of claim 1 , wherein the plurality of timed circuits comprise a plurality of channels.

10. The computer-implemented method of claim 1 , wherein the plurality of channels are all of the same I/O type.

11. The computer-implemented method of claim 1 , wherein the plurality of channels comprise multiple I/O types.

12. The computer-implemented method of claim 1 , wherein timing and triggering for the plurality of timed circuits is homogeneous.

13. The computer-implemented method of claim 1 , wherein timing and triggering for the plurality of timed circuits is heterogeneous.

14. The computer-implemented method of claim 1 , wherein the I/O operation comprises a read operation from one or more of the plurality of timed circuits, and wherein said executing the graphical program to perform the I/O operation comprises the graphical program issuing a read request for a specified input type.

15. The computer-implemented method of claim 14 , the method further comprising:

in response to the read request, the software performing:

determining one or more of the plurality of timed circuits to read to satisfy the read request;

reading data from the determined one or more timed circuits;

formatting the data into an order expected by the graphical program; and

returning the data to the graphical program.

16. The computer-implemented method of claim 1 , wherein the I/O operation comprises a write operation to one or more of the plurality of timed circuits, and wherein said executing the graphical program to perform the I/O operation comprises the graphical program issuing a write request for a specified output type.

17. The computer-implemented method of claim 16 , the method further comprising:

in response to the write request, the software performing:

determining one or more of the plurality of timed circuits to write to in order to satisfy the write request;

receiving data from the graphical program;

formatting the data into an order required by the timed circuits; and

writing the data to the determined one or more timed circuits.

18. The computer-implemented method of claim 1 ,

wherein the graphical program comprises a plurality of interconnected nodes that visually indicate functionality of the graphical program.

19. The computer-implemented method of claim 1 , wherein said creating the graphical program comprises:

arranging a plurality of nodes on a display; and

interconnecting the plurality of nodes in response to user input.

20. The computer-implemented method of claim 1 ,

wherein the graphical program comprises a block diagram portion and a user interface portion.

21. The computer-implemented method of claim 20 ,

wherein, during execution of the graphical program, the graphical user interface is displayed on a display of a first computer system and the block diagram executes on a second computer system.

22. The computer-implemented method of claim 1 ,

wherein the graphical program comprises a graphical data flow program.

23. The computer-implemented method of claim 1 ,

wherein the graphical program is operable to perform one or more of:

an industrial automation function;

a process control function;

a test and measurement function; and

a simulation function.

24. The computer-implemented method of claim 1 , wherein the software comprises driver software.

25. A memory medium which stores program instructions for automatic synchronization of I/O devices, wherein the program instructions are executable by a processor to implement:

a graphical program, wherein the graphical program specifies configuration and operation of a plurality of timed circuits comprised on one or more I/O devices;

wherein the program instructions are further executable to implement:

executing the graphical program to perform an I/O operation using the one or more I/O devices, wherein said executing comprises invoking software to perform:

analyzing the plurality of timed circuits to determine timing and triggering information for synchronous operation of the plurality of timed circuits, wherein said analyzing comprises:

determining the number and types of timing signals for each of the plurality of timed circuits;

determining sharing of the timing signals in order to synchronize the timed circuits;

determining sources of timing signals for each of the plurality of timed circuits;

determining timing signal routes from each of the sources to the plurality of timed circuits; and

determining a starting order of the plurality of timed circuits;

configuring the timed circuits in accordance with the timing and triggering information; and

operating the configured plurality of timed circuits to perform the I/O operation in a synchronous manner, wherein said operating the plurality of timed circuits comprises:

initiating operation of each of the plurality of timed circuits in accordance with the determined starting order.

26. A system for automatic synchronization of I/O devices, comprising:

a computer system, comprising:

a processor; and

a memory medium coupled to the processor;

one or more I/O devices coupled to the processor and memory medium;

wherein the memory medium stores a graphical program, wherein the graphical program specifies configuration and operation of a plurality of timed circuits comprised on the one or more I/O devices, and wherein the graphical program is executable to perform an I/O operation using the one or more I/O devices;

wherein, in being executable, the graphical program is executable to invoke software to perform:

analyzing the plurality of timed circuits to determine timing and triggering information for synchronous operation of the plurality of timed circuits, wherein said analyzing comprises:

determining the number and types of timing signals for each of the plurality of timed circuits;

determining sharing of the timing signals in order to synchronize the timed circuits;

determining sources of timing signals for each of the plurality of timed circuits;

determining timing signal routes from each of the sources to the plurality of timed circuits; and

determining a starting order of the plurality of timed circuits;

configuring the timed circuits in accordance with the timing and triggering information; and

operating the configured plurality of timed circuits to perform the I/O operation in a synchronous manner, wherein said operating the plurality of timed circuits comprises:

initiating operation of each of the plurality of timed circuits in accordance with the determined starting order.

27. A method for automatic synchronization of I/O devices, comprising:

creating a graphical program, wherein the graphical program specifies configuration and operation of a plurality of timed circuits comprised on one or more I/O devices;

executing the graphical program to perform an I/O operation using the one or more I/O devices, wherein said executing comprises invoking software to perform:

determining the plurality of timed circuits, wherein each of the plurality of timed circuits comprises one of:

an input circuit comprising one or more input channels, wherein the input circuit is operable to read data from the one or more input channels and provide the data to the graphical program; and

an output circuit comprising one or more output channels, wherein the output circuit is operable to receive data from the graphical program and write the data to the one or more output channels;

determining the number and types of timing signals for each of the plurality of timed circuits;

determining sharing of the multiplicity of timing signals in order to synchronize the timed circuits;

determining sources of timing signals for each of the plurality of timed circuits;

determining timing signal routes from each of the sources to the plurality of timed circuits;

determining a starting order of the plurality of timed circuits;

initiating operation of each of the plurality of timed circuits in accordance with the determined starting order;

determining a stopping order of the plurality of timed circuits; and

terminating operation of each of the plurality of timed circuits in accordance with the determined stopping order.