PLL circuit having reduced capacitor size

1. A PLL circuit comprising

a voltage controlled oscillator (VCO), a phase error detector (PED) for detecting a phase error between an output signal from said voltage controlled oscillator (VCO) divided by a frequency divider (DIV) and a reference signal (fin), and a loop filter (LF) inserted between an error signal output of said phase error detector (PED) and a control input of said voltage controlled oscillator (VCO), wherein said loop filter (LF) comprises

two charge pumps (C P1 , C P2 ), each delivering a respective output current (I CP1 , I CP2 ) according to a level of the error signal at said error signal output,

a first resistor (R 2 ) and a first transistor (N 2 ), the first resistor (R 2 ) having a first terminal connected to a first supply potential (V+) and the first transistor (N 2 ) having a current path connected between a second terminal of the first resistor (R 2 ) and a second supply potential (GND),

a capacitor (C′), a first electrode of which is connected to the current output of the first charge pump (C P1 ) and a second electrode of which is connected to one of said supply potentials (V+), and

a control circuit (OA, N 1 , R 1 ) having an input connected to the first electrode of said capacitor (C′) and an output connected to a control electrode of said first transistor (N 2 ), for controlling the equivalent resistance of the first transistor (N 2 ) so that said equivalent resistance divided by the resistance value of the first resistor (R 2 ) equals the potential difference between said second supply potential (GND) and said first electrode of said capacitor (C′) divided by the potential difference (VC′) between said first supply potential (V+) and said first electrode of said capacitor (C′),

an intermediate point between said first resistor (R 2 ) and said first transistor (N 2 ) being connected to a current output of said second charge pump (C P2 ) and connected to the control voltage input of the voltage controlled oscillator and the output current of the first charge pump (C P1 ) for a given level of the error signal being less than the output current of the second charge pump (C P2 ).

2. The PLL circuit of claim 1 , wherein the control circuit comprises a second resistor (R 1 ) and a second transistor (N 1 ) connected in series between said first and second supply potentials and an operational amplifier (OA) having an output connected to control electrodes of said first and second transistors (N 1 , N 2 ), a non-inverting input connected to an intermediate point between said second resistor (R 1 ) and said second transistor (N 1 ), and an inverting input connected to the current output of the first charge pump (C P1 ).

3. The PLL circuit of claim 2 , wherein said first and second resistors (R 1 R 2 ) are identical in resistance and said first and second transistors (N 1 , N 2 ) have identical values of ON resistance.

4. In a PLL circuit, a control loop for an input to a VCO comprising:

first and second charge pumps each having an output coupled to the input of the VCO;

an RC network having a first resistance and a capacitance and being coupled to the output of the first charge pump;

a second resistance coupled between the output of the first charge pump and the input to the VCO, wherein the value of the capacitance C is reduced by a factor X, where

V

VCO

=

x

C

′

⁢

I

CP

⁢

⁢

2

⁢

t

+

I

CP

⁢

⁢

2

⁢

R

⁢

⁢

2

and

V VCO =VCO input voltage

I cp2 is the current output by the second charge pump

R 2 =second resistance

C′=new capacitance value=C*X

C=original capacitance value.

5. In a PLL circuit, a control loop for an input to a (VCO) comprising:

first and second charge pumps each having an output coupled to the input of the (VCO);

an RC network having a first resistance and a capacitance and being coupled to the output of the first charge pump;

a second resistance coupled between the output of the first charge pump and the input to the (VCO), wherein the value of the capacitance C is reduced by a factor x, where

V

VCO

=

1

C

′

⁢

I

CP

⁢

⁢

1

⁢

t

+

I

CP

⁢

⁢

2

⁢

R

and

I cp1 =x=is the current output by the first charge pump

I cp2 =0<x<1=current output of second charge pump

V VCO =VCO input voltage

C′=new capacitance value=C*X

C=original capacitance value.