Liquid crystal display device including polycrystalline silicon thin film transistor and method of fabricating the same

1. A liquid crystal display device having a switching element in a pixel portion and a CMOS element in a driving portion, comprising:

a substrate;

a gate electrode on the substrate;

a gate insulating layer on the gate electrode;

a polycrystalline silicon layer on the gate insulating layer, the polycrystalline silicon layer having an active region in a central portion corresponding to the gate electrode and an ohmic contact region at side portions of the active region;

an interlayer insulating layer having a set of contact holes for contacting the polycrystalline silicon layer at the side portions, the interlayer insulating layer entirely contacting the polycrystalline silicon layer in the active region without an intervening layer;

source and drain electrodes spaced apart from each other directly on the interlayer insulating layer, the source and drain electrodes contacting the polycrystalline silicon layer through the set of contact holes; and

a pixel electrode directly on the drain electrode,

wherein ends of the interlayer insulating layer coincide with ends of the polycrystalline silicon layer, and wherein ends of the source and drain electrodes are disposed within the ends of the interlayer insulating layer.

2. The device of claim 1 , further comprising LDD regions between the active region and the ohmic contact region.

3. The device of claim 1 , wherein the ohmic contact region is doped with one of n-type impurities and p-type impurities.

4. An array substrate for a liquid crystal display device, comprising:

a substrate;

gate electrodes on the substrate;

a gate insulating layer on the gate electrode;

polycrystalline silicon layers on the gate insulating layer, each of the polycrystalline silicon layers having an active region in a central portion corresponding to each of the gate electrodes and an ohmic contact region at side portions of the active region;

interlayer insulating layers on the polycrystalline silicon layers in which ends of the interlayer insulating layers coincide with ends of the polycrystalline silicon layers, each of the interlayer insulating layers entirely contacting each of the polycrystalline silicon layers in the active region without an intervening layer;

sets of contact holes for contacting the polycrystalline silicon layers;

pairs of source and drain electrodes spaced apart from each other directly on the interlayer insulating layers contacting the polycrystalline silicon layers through the sets of contact holes; and

pixel electrodes each directly on the drain electrode of each pair of the source and drain electrodes,

wherein ends of the pairs of source and drain electrodes are disposed within the ends of the interlayer insulating layers.

5. The device of claim 4 , wherein the gate insulating layer is exposed between adjacent polycrystalline silicon layers.