Adjusting power consumption of digital circuitry relative to critical path circuit having the largest propagation delay error
View Patent ↗A method and apparatus is disclosed for adjusting at least one of a supply voltage and a clocking frequency applied to digital circuitry of a computing device, wherein the digital circuitry comprises a plurality of critical path circuits and a corresponding plurality of propagation delay error circuits. Each propagation delay error circuit generates a propagation delay error signal representing an error in propagation delay for the corresponding critical path circuit. The computing device further comprises a voting circuit for comparing the propagation delay error signals in order to select the largest propagation delay error signal for use in adjusting the at least one of the supply voltage and clocking frequency.
1. A computing device comprising:
(a) digital circuitry including a plurality of critical path circuits and a corresponding plurality of propagation delay error circuits, wherein each propagation delay error circuit generates a propagation delay error signal representing an error in propagation delay for the corresponding critical path circuit;
(b) a voting circuit for comparing the propagation delay error signals in order to select the largest propagation delay error signal; and
(c) an adjustable circuit, responsive to the largest propagation delay error signal, for adjusting at least one of a supply voltage and a clocking frequency applied to the critical path circuits.
2. The computing device as recited in claim 1 , wherein each propagation delay error circuit comprises:
(a) a matched delay circuit substantially matched to the corresponding critical path circuit;
(b) a periodic input signal applied to an input of the matched delay circuit; and
(c) a phase comparator for computing a phase difference between the periodic input signal and an output of the matched delay circuit.
3. The computing device as recited in claim 1 , wherein each propagation delay error circuit comprises:
(a) a propagation delay circuit for generating a propagation delay frequency representing a propagation delay of the corresponding critical path circuit; and
(b) a frequency comparator for generating a frequency error signal representing a difference between a reference frequency and the propagation delay frequency.
4. The computing device as recited in claim 3 , wherein at least one of the propagation delay error circuits scales at least one of the reference frequency and the propagation delay frequency.
5. The computing device as recited in claim 1 , wherein:
(a) each propagation delay error signal comprises a pulse width modulated signal; and
(b) the voting circuit comprises an OR gate for ORing the propagation delay error signals.
6. The computing device as recited in claim 1 , wherein:
(a) each propagation delay error signal comprises a multiple-bit digital signal; and
(b) the voting circuit comprises a digital comparator for comparing the propagation delay error signals.
7. A method of adjusting at least one of a supply voltage and a clocking frequency applied to digital circuitry of a computing device, the digital circuitry comprising a plurality of critical path circuits, the method comprising the steps of:
(a) generating a plurality of propagation delay error signals each representing an error in propagation delay for a corresponding one of the critical path circuits;
(b) comparing the propagation delay error signals in order to select the largest propagation delay error signal; and
(c) adjusting at least one of the supply voltage and the clocking frequency in response to the largest propagation delay error signal.
8. The method as recited in claim 7 , wherein the step of generating one of the propagation delay error signals comprises the steps of:
(a) applying a periodic input signal to an input of a matched delay circuit, wherein the matched delay circuit is substantially matched to the corresponding critical path circuit; and
(b) computing a phase difference between the periodic input signal and an output of the matched delay circuit.
9. The method as recited in claim 7 , wherein the step of generating one of the propagation delay error signals comprises the steps of:
(a) generating a propagation delay frequency representing a propagation delay of the corresponding critical path circuit; and
(b) generating a frequency error signal representing a difference between a reference frequency and the propagation delay frequency.
10. The method as recited in claim 9 , wherein the step of generating one of the propagation delay error signals further comprises the step of scaling at least one of the reference frequency and the propagation delay frequency.
11. The method as recited in claim 7 , wherein:
(a) each propagation delay error signal comprises a pulse width modulated signal; and
(b) the step of selecting the largest propagation delay error signal comprises the step of ORing the propagation delay error signals.
12. The method as recited in claim 7 , wherein:
(a) each propagation delay error signal comprises a multiple-bit digital signal; and
(b) the step of comparing the propagation delay error signals in order to select the largest propagation delay error signal comprises the step of comparing the multi-bit digital signals.