Boost signal interface method and apparatus
An apparatus and method for providing a boost signal to a pixel array that includes a plurality of rows are described. The apparatus includes a first input that receives a boost signal. The apparatus also includes a second input that receives at least one control signal and a third input that receives a reset enable signal. The apparatus also includes a plurality of outputs. Each output is coupled to a corresponding row of the pixel array. The apparatus selectively provides the boost signal at one of the outputs based on the control signal and the reset enable signal.
1 . An apparatus for providing a boost signal to a pixel array that includes a plurality of rows, the apparatus comprising:
a) a first input that receives a boost signal;
b) a second input that receives at least one control signal;
c) a third input that receives a reset enable signal;
d) a plurality of outputs; wherein each output is coupled to a corresponding row of the pixel array; wherein the boost signal is selectively provided at one of the outputs based on the control signal and the reset enable signal.
2 . The apparatus of claim 1 wherein the apparatus includes a hierarchical switching structure that includes
a plurality of first level switches; wherein each switch includes an input that receives the boost signal, an input that receives a switch control signal and an output that provides the boost signal based on the switch control signal; and
a plurality of second level multiplexers; wherein each multiplexor includes an input coupled to the output of a respective first level switch that receives the boost signal, a second input that receives a multiplexor control signal, and a plurality of outputs; wherein one of the outputs provides the boost signal based on the multiplexer control signal.
3 . The apparatus of claim 1 wherein the pixel array includes a plurality of rows that are not selected at any one time; wherein the non-selected row each includes a parasitic capacitance, the apparatus further comprising:
an effective parasitic capacitance reduction mechanism that isolates the first input from the parasitic capacitance of a plurality of non-selected rows.
4 . The apparatus of claim 1 wherein the apparatus is incorporated in one of mobile camera handsets, video telephones, personal digital assistants, image-enabled appliances, digital still mini cameras, embedded automotive applications, and monitoring equipment.
5 . The apparatus of claim 2 wherein the hierarchical switching structure minimizes row-to-row offsets.
6 . The apparatus of claim 2 wherein the hierarchical switching structure includes a logic circuit for each first level switch that receives selected bits from a row address and based thereon generates a control signal for controlling the respective first level switch; wherein the hierarchical switching structure includes a logic circuit for each second level switch that receives selected bits from a row address and based thereon generates a control signal for controlling the respective first level switch.
7 . The apparatus of claim 2 wherein the hierarchical switching structure minimizes area utilized by the boost signal interface mechanism.
8 . A camera module comprising:
optics;
an image sensor that includes a pixel array that includes a plurality of rows;
an image processor;
a boost signal generator;
a boost signal interface mechanism that includes
a first input coupled to the boost signal generator that receives a boost signal;
a second input that receives at least one control signal;
a third input that receives a reset enable signal;
a plurality of outputs; wherein each output is coupled to a corresponding row of the pixel array; wherein the boost signal is selectively provided at one of the outputs based on the control signal and the reset enable signal.
9 . The camera module of claim 8 wherein the boost signal interface mechanism includes a hierarchical switching structure that includes
a plurality of first level switches; wherein each switch includes an input that receives the boost signal, an input that receives a switch control signal and an output that provides the boost signal based on the switch control signal; and
a plurality of second level multiplexers; wherein each multiplexor includes an input coupled to the output of a respective first level switch that receives the boost signal, a second input that receives a multiplexor control signal, and a plurality of outputs; wherein one of the outputs provides the boost signal based on the multiplexer control signal.
10 . The system of claim 8 wherein the pixel array includes a plurality of rows that are not selected at any one time; wherein the non-selected row each includes a parasitic capacitance, the boost signal interface mechanism further comprising:
an effective parasitic capacitance reduction mechanism that isolates the first input from the parasitic capacitance of a plurality of non-selected rows.
11 . The system of claim 8 wherein the apparatus is incorporated in one of mobile camera handsets, video telephones, personal digital assistants, image-enabled appliances, digital still mini cameras, embedded automotive applications, monitoring equipment.
12 . The system of claim 9 wherein the hierarchical switching structure minimizes row-to-row offsets.
13 . The system of claim 9 wherein the hierarchical switching structure minimizes parasitic capacitance of the boost signal interface mechanism.
14 . The system of claim 9 wherein the hierarchical switching structure minimizes area utilized by the boost signal interface mechanism.
15 . A method for providing a boost signal to an array that includes a plurality of pixels; wherein the pixels are arranged in rows; wherein the method includes:
providing a boost signal interface mechanism that is coupled to the pixel array;
the boost signal interface mechanism receiving a boost signal;
the boost signal interface mechanism receiving at least one control signal;
the boost signal interface mechanism receiving a reset enable signal; and
boost signal interface mechanism selectively providing the boost signal to one of the rows of the pixel array based on the control signal and the reset enable signal.
16 . The method of claim 15 wherein providing a boost signal interface mechanism that is coupled to the pixel array includes;
providing a boost signal interface mechanism that includes a hierarchical switching structure; wherein the hierarchical switching structure includes a first set of switches and a second set of multiplexers; wherein each multiplexer is coupled to a corresponding switch.
17 . The method of claim 16 wherein the boost signal interface mechanism receiving at least one control signal includes
receiving at least one switch control signal for each switch; and
receiving at least one multiplexer control signal for each multiplexer.
18 . The method of claim 16 wherein the hierarchical switching structure minimizes row-to-row offsets.
19 . The method of claim 16 wherein the hierarchical switching structure minimizes parasitic capacitance of the boost signal interface mechanism.
20 . The method of claim 16 wherein the hierarchical switching structure conserves area by utilized by the boost signal interface mechanism.