Semiconductor memory, method of testing semiconductor memory and method of manufacturing semiconductor memory
View Patent ↗Testing circuits each including a comparator for comparing data read from semiconductor memories to be tested with expected value data and thereby detecting coincidences/non-coincidences, and a counter for counting the number of non-coincidences detected are provided on a printed board for burn-in or within semiconductor memories to be tested. The semiconductor memories can be tested by the testing circuits respectively.
1. A nonvolatile memory apparatus comprising:
a nonvolatile memory array having a plurality of nonvolatile memory cells;
control circuitry having a first circuit and a second circuit;
an address generation circuit; and
a plurality of word lines, each of which is coupled to corresponding ones of said nonvolatile memory cells,
wherein said control circuit controls a first operation in response to receiving a command from outside thereof,
wherein in said first operation, said control circuit performs control such that:
said address generation circuit generates a first address for selecting one word line,
said first circuit operates to cause first data to be stored into nonvolatile memory cells coupled to said one word line, and then to cause data to be read from said nonvolatile memory cells coupled to said one word line,
said second circuit compares said data read from said nonvolatile memory cells coupled to said one word line and expectancy data in accordance with said first data, and stores said first address when said data and said expectancy data do not match, and
said address generation circuit generates a second address, different from said first address, for selecting another one of said word lines after storing said first address.
2. A nonvolatile memory apparatus according to claim 1 , further comprising a volatile memory,
wherein said first address is stored to said volatile when said data read from said nonvolatile memory cells coupled to said one word line and said expectancy data do not match.
3. A nonvolatile memory apparatus according to claim 2 ,
wherein said control circuit repeats said first operation until all of said plurality of word lines are selected by said address generation circuit.
4. A nonvolatile memory apparatus according to claim 3 ,
wherein said command is a test command for testing said plurality of memory cells in said memory array.
5. A nonvolatile memory apparatus according to claim 4 ,
wherein said first data and said expectancy data are received from outside the apparatus.
6. A nonvolatile memory apparatus according to claim 4 ,
wherein said first data and said expectancy data are generated internally of the apparatus.