Dynamic impedance compensation circuit and method
View Patent ↗An impedance compensation circuit generates per-group pull-up impedance information and per-group pull-down impedance information to calibrate a plurality of input/output pads and dynamically updates impedance information on a per channel basis. A group refers to a group of I/O pads having similar output drive strengths in a channel. A channel refers to all I/O pads, which collectively provide a bus interface to an external device. For example, all the I/O pads interfacing with a memory module may be grouped into a channel, and address I/O pads in a channel may be arranged into a “group.” Memory I/O pads may be grouped together into a channel since memory interface pads have input/output characteristics that may be different from those of other types of I/O pads in the chip. According to one embodiment, per-group programmable offset information provides calibration information that may be different for each group in each channel.
1. An impedance compensation circuit for a plurality of input/output pads comprising:
a programmable impedance information circuit operative to generate per-group programmable impedance information corresponding with the plurality of input/output pads, wherein the plurality of input/output pads are associated with a plurality of channels; and
a channel-specific impedance calibration circuit, operatively coupled to the programmable impedance information circuit, a plurality of pull-up channel pads and a plurality of pull-down channel pads, and operative to receive the per-group programmable impedance information, and in response to generate per-channel pull-up impedance information and per-channel pull-down impedance information for each channel.
2. The impedance compensation circuit of claim 1 wherein the input/output pads having similar output drive strengths are associated with a corresponding group of a channel.
3. The impedance compensation circuit of claim 1 wherein the channel specific impedance calibration circuit is operative to receive the per-group programmable impedance information corresponding with an impedance change in at least one of the input/output pads, and in response dynamically change at least one of the per-channel pull-up impedance information and the per-channel pull-down impedance information in response to the received per-group programmable impedance information.
4. The impedance compensation circuit of claim 1 wherein the channel-specific impedance calibration circuit dynamically changes at least one of: the per-channel pull-up impedance information and the per-channel pull-down impedance information during at least one of: a memory idle mode and a memory refresh mode.
5. An impedance compensation circuit for a plurality of pull-up channel pads and a plurality of pull-down channel pads comprising:
a base impedance calibration information generator operative to produce pull-up base impedance information and pull-down base impedance information for the plurality of pull-up channel pads and the plurality of pull-down channel pads;
a plurality of per-group programmable offset registers operative to produce per-group programmable offset information; and
a channel-specific impedance calibration circuit, operatively coupled to the base impedance information generator, the plurality of per-group programmable offset registers, the plurality of pull-up channel pads and the plurality of pull-down channel pads, and operative to receive the pull-up base impedance information, the pull-down base impedance information and the per-group programmable offset information, and in response to produce per-channel pull-up impedance information and per-channel pull-down impedance information, wherein the plurality of pull-up channel pads and the plurality of pull-down channel pads are associated with a plurality of channels.
6. The impedance compensation circuit of claim 5 wherein the channel-specific impedance calibration circuit is operative to add the pull-up base impedance information and the pull-down base impedance information with the corresponding per-group programmable offset information, to produce the per-channel pull-up impedance information and the per-channel pull-down impedance information.
7. The impedance compensation circuit of claim 5 wherein the input/output pads having similar output drive strengths are associated with a corresponding group of a channel.
8. The impedance compensation circuit of claim 5 wherein the base impedance information generator dynamically changes the pull-up base impedance information and the pull-down base impedance information in response to an impedance change in at least one of the pull-up channel pads and the pull-down channel pads.
9. The impedance compensation circuit of claim 5 wherein the base impedance calibration information generator dynamically changes the per-channel pull-up impedance information and the per-channel pull-down impedance information during at least one of: a memory idle mode and a memory refresh mode.
10. An impedance compensation circuit for a plurality of input/output pads comprising:
an impedance matching calibration circuit operative to receive at least a pull-up impedance match drive signal and a pull-down impedance match drive signal, and in response generate pull-up strength feedback information and pull-down strength feedback information;
an impedance controller circuit, operatively coupled to the impedance matching calibration circuit and operative to receive the pull-up strength feedback information and the pull-down strength feedback information, and in response generate pull-up base impedance information and pull-down base impedance information for the plurality of input/output pads, and operative to generate the pull-up impedance match drive signal and the pull-down impedance match drive signal;
a plurality of per-group programmable offset registers operative to generate per-group programmable offset information; and
a channel-specific impedance calibration circuit, operatively coupled to the impedance controller circuit, the plurality of per-group programmable offset registers, a plurality of pull-up channel pads and a plurality of pull-down channel pads, and operative to receive the pull-up base impedance information, the pull-down base impedance information and the per-group programmable offset information, and in response to generate per-channel pull-up impedance information and per-channel pull-down impedance information, wherein the plurality of pull-up channel pads and the plurality of pull-down channel pads are associated with a plurality of channels.
11. The impedance compensation circuit of claim 10 wherein in response to the impedance controller circuit being operative to generate the pull-up base impedance information and the pull-down base impedance information, the impedance controller is operative to provide an updated pull-up impedance match drive signal and an updated pull-down impedance match drive signal to the impedance matching calibration circuit.
12. A method of impedance compensation for a plurality of input/output pads comprising:
receiving per-group programmable impedance information corresponding with the plurality of input/output pads, wherein the plurality of input/output pads are associated with a plurality of channels; and
generating per-channel pull-up impedance information and per-channel pull-down impedance information for each channel in response to the received per-group programmable impedance information.
13. The method of claim 12 wherein the input/output pads having similar output drive strengths are associated with a corresponding group of a channel.
14. The method of claim 12 including dynamically changing at least one of: the per-channel pull-up impedance information and the per-channel pull-down impedance information in response to an impedance change associated with the per-group programmable impedance information.
15. The method of claim 12 including dynamically changing at least one of the per-channel pull-up impedance information and the per-channel pull-down impedance information during at least one of: a memory idle mode and a memory refresh mode.
16. A method of impedance compensation for a plurality of pull-up channel pads and a plurality of pull-down channel pads comprising:
receiving pull-up base impedance information and pull-down base impedance information for the plurality of pull-up channel pads and the plurality of pull-down channel pads;
receiving per-group programmable offset information corresponding with the plurality of pull-up channel pads and the plurality of pull-down channel pads, wherein the plurality of pull-up channel pads and the plurality of pull-down channel pads are associated with a plurality of groups of a channel; and
generating per-channel pull-up impedance information and per-channel pull-down impedance information for each channel in response to the produced pull-up base impedance information, the pull-down base impedance information and the per-group offset information.
17. The method of claim 16 including:
adding the pull-up base impedance information and the per-group programmable offset information to produce the per-channel pull-up impedance information; and
adding the pull-down base impedance information and the per-group programmable offset information to produce the per-channel pull-down information.
18. The method of claim 16 wherein the pull-up channel pads and the pull-down channel pads having similar output drive strengths are associated with a corresponding group of a channel.
19. The method of claim 16 including:
dynamically changing the pull-up base impedance information and the pull-down base impedance information in response to an impedance change associated with at least one of: the pull-up base impedance information and the pull-down base impedance information.
20. The method of claim 16 including:
dynamically changing the per-channel pull-up impedance information and the per-channel pull-down impedance information during at least one of: a memory idle mode and a memory refresh mode.
21. Memory containing instructions executable by one or more processing devices that cause the one or more processing devices to:
receive per-group programmable impedance information corresponding with a plurality of input/output pads, wherein the plurality of input/output pads are associated with a plurality of groups of a channel; and
produce per-channel pull-up impedance information and per-channel pull-down impedance information for each channel.
22. The memory of claim 21 containing executable instructions that causes the one or more processing devices to:
dynamically change at least one of: the per-channel pull-up impedance information and the per-channel pull-down impedance information in response to an impedance change associated with at least one of the pull-up base impedance information and the pull-down base impedance information.
23. A graphics processing integrated circuit comprising:
an impedance compensation circuit for a plurality of input/output pads comprising:
a programmable impedance information circuit operative to generate per-group programmable impedance information corresponding with the plurality of input/output pads, wherein the plurality of input/output pads are associated with a plurality of channels;
a channel-specific impedance calibration circuit, operatively coupled to the programmable impedance information circuit, a plurality of pull-up channel pads and a plurality of pull-down channel pads, and operative to receive the per-group programmable impedance information, and in response to generate per-channel pull-up impedance information and per-channel pull-down impedance information for each channel; and
a graphics processor operatively coupled to the plurality of input/output pads.
24. The graphics processing integrated circuit of claim 23 wherein the input/output pads having similar output drive strengths are associated with a corresponding group of a channel.
25. A memory circuit comprising:
an impedance compensation circuit for a plurality of input/output pads comprising:
a programmable impedance information circuit operative to generate per-group programmable impedance information corresponding with the plurality of input/output pads, wherein the plurality of input/output pads are associated with a plurality of channels;
a channel-specific impedance calibration circuit, operatively coupled to the programmable impedance information circuit, a plurality of pull-up channel pads and a plurality of pull-down channel pads, and operative to receive the per-group programmable impedance information, and in response to generate per-channel pull-up impedance information and per-channel pull-down impedance information for each channel; and
memory operatively coupled to the plurality of input/output pads.
26. The memory circuit of claim 25 wherein the input/output pads having similar output drive strengths are associated with a corresponding group of a channel.
27. The programmable impedance information circuit of claim 1 wherein the per-group programmable impedance information comprises pull-up base impedance information, pull-down base impedance information and per-group programmable offset information.
28. The programmable impedance information circuit of claim 1 wherein the plurality of input/output pads are associated with a plurality of channels based on a common calibration setting for a plurality of groups wherein at least two groups of input/output pads have different drive strengths.