Reduced signal swing in bit lines in a CAM
View Patent ↗A Content Addressable Memory device with a bit line that is driven between first and second voltage levels depending on the state of a logic signal applied thereto. The magnitude of the voltage swing between the first and second voltage levels is reduced in comparison to other voltages of the Content Addressable Memory device, or in comparison to the voltage swing of prior art bit lines, so that effects associated with power dissipation by the bit line are reduced. The memory includes a plurality of match lines and a plurality of bit lines, each of the plurality of bit lines coupled to a bit line driver circuit adapted to provide a bit line voltage with reduced signal swing.
1. A method of driving a bit line of a content addressable memory, the method comprising:
providing a driver circuit having first and second terminals, the driver circuit coupled to a constant electrical potential and a ground potential, the second terminal connected to a bit line of a content addressable memory;
receiving a first signal corresponding to a first logic state at the first terminal of the driver circuit;
setting the bit line to a first voltage in response to the first signal;
receiving a second signal corresponding to a second logic state at the first terminal;
setting the bit line to a second voltage in response to the second signal, the difference between the first and second potential being less than the difference between the ground potential and the constant electrical potential.
2. The method of claim 1 , wherein providing a driver circuit comprises providing an inverter circuit.
3. The method of claim 2 , wherein receiving the second signal comprises receiving the second signal at a gate of a p-type transistor, a drain of the p-type transistor being coupled to a drain of an n-type transistor, a source of the p-type transistor and a gate of the n-type transistor being coupled to the constant electrical potential, and wherein the first potential is approximately the ground potential and the second potential is approximately the constant electrical potential minus the threshold voltage of the n-type transistor.
4. The method of claim 1 , wherein difference between the first and second potential is between a ground potential and a value less than the constant electrical potential.
5. The method of claim 1 , wherein difference between the first and second potential is between a value greater than the ground potential and the constant electrical potential.
6. The method of claim 2 , wherein receiving the second signal comprises receiving the second signal at a gate of a first n-type transistor, the first n-type transistor having a drain coupled to a drain of a first p-type transistor and a gate of a second p-type transistor and having a source coupled to a drain of the second p-type transistor, a drain of a second n-type transistor, and the second terminal, the sources of the first and second p-type transistors are coupled to the constant electrical potential, and wherein the first potential is approximately the ground potential and the second potential is approximately the constant electrical potential minus the threshold voltage of the first p-type transistor.
7. The method of claim 2 , wherein receiving the second signal comprises receiving the second signal at gate of a p-type transistor, the p-type transistor having a source coupled to the constant electrical potential and a drain coupled to a diode, the diode coupled between the p-type transistor drain and the second terminal in forward-biased orientation, and wherein and wherein the first potential is approximately the ground potential and the second potential is approximately the constant electrical potential minus the forward voltage drop across the diode.
8. The method of claim 2 , wherein receiving the second signal comprises receiving the second signal at gate of a n-type transistor, the n-type transistor having a source coupled to the ground potential and a drain coupled to a diode, and wherein and wherein the first potential is a value above the ground potential and the second potential is approximately the constant electrical potential.
9. A method of operating a content addressable memory, the method comprising:
supplying a first voltage to a plurality of non-inverting bit line drivers, the plurality of non-inverting bit line drivers respectively coupled to a plurality of un-complemented bit lines;
supplying the first voltage to a plurality of inverting bit line drivers, the plurality of inverting bit line drivers respectively coupled to a plurality of complemented bit lines;
supplying a second voltage to a plurality of match line drivers, the plurality of match line drivers respectively coupled to a plurality of match lines, the first voltage being lower than the second voltage.
10. A method of operating a content addressable memory, the method comprising:
charging a match line of said content addressable memory to a first voltage, said first voltage measured with respect to a second reference voltage;
applying a logic signal to an input of a bit line driver so that said bit line driver sets a bit line to one of a third or a fourth voltage, a difference between the third voltage and the fourth voltage being less than a difference between the second reference voltage and the first voltage;
comparing a logic state of a first bit stored in said content addressable memory with a value of said logic signal; and
changing the voltage level of said match line to said second reference potential if said logic state of said first bit is not equal to said value of said logic signal.
11. The method of claim 10 , wherein the third voltage is approximately equal to the second voltage and the fourth voltage is lower than the first voltage.
12. The method of claim 10 , wherein the third voltage is a value greater than the second voltage and the fourth voltage is approximately equal to the first voltage.