Adjusting power consumption of digital circuitry by generating frequency error representing error in propagation delay
View Patent ↗A method and apparatus is disclosed for adjusting at least one of a supply voltage and a clocking frequency applied to digital circuitry of a computing device, wherein the digital circuitry comprises a critical path circuit. A propagation delay frequency representing a propagation delay of the critical path circuit is generated, and a frequency error signal is generated representing a difference between a reference frequency and the propagation delay frequency. At least one of the supply voltage and the clocking frequency is adjusted in response to the frequency error signal.
1. A computing device comprising:
(a) digital circuitry including a critical path circuit;
(b) a propagation delay circuit for generating a propagation delay frequency representing a propagation delay of the critical path circuit;
(c) a reference frequency;
(d) a frequency comparator for generating a frequency error signal representing a difference between the reference frequency and the propagation delay frequency; and
(e) an adjustable circuit, responsive to the frequency error signal, for adjusting at least one of a supply voltage a power source and a clocking frequency applied to the critical path circuit.
2. The computing device as recited in claim 1 , wherein the propagation delay circuit comprises a matched delay oscillator.
3. The computing device as recited in claim 2 , wherein the matched delay oscillator comprises a plurality of matched delay circuits connected in series in order to scale the propagation delay frequency, wherein each matched delay circuit substantially matches the critical path circuit.
4. The computing device as recited in claim 1 , further comprising an integrator for generating an integrated frequency error signal, wherein the adjustable circuit is responsive to the integrated frequency error signal.
5. The computing device as recited in claim 4 , further comprising:
(a) a scalar for generating a proportional frequency error signal; and
(b) an adder for adding the integrated frequency error signal to the proportional frequency error signal to generate a proportional/integral frequency error signal, wherein the adjustable circuit is responsive to the proportional/integral frequency error signal.
6. The computing device as recited in claim 4 , wherein the integrator comprises discrete-time circuitry.
7. The computing device as recited in claim 4 , wherein the integrated frequency error signal is a discrete-time signal.
8. The computing device as recited in claim 7 , further comprising conversion circuitry for converting the integrated frequency error signal into a continuous-time signal, wherein the adjustable circuit is responsive to the continuous-time signal.
9. The computing device as recited in claim 1 , wherein:
(a) the frequency comparator comprises an up/down counter;
(b) the up/down counter is clocked by the reference frequency for a first interval; and
(c) the up/down counter is clocked by the propagation delay frequency for a second interval.
10. The computing device as recited in claim 9 , wherein at least one of the first and second intervals is programmable.
11. The computing device as recited in claim 9 , wherein the up/down counter outputs a pulse width modulated (PWM) signal having a duty cycle proportional to the difference between the reference frequency and the propagation delay frequency.
12. The computing device as recited in claim 11 , further comprising a filter for filtering the PWM signal.
13. The computing device as recited in claim 1 , wherein the frequency error signal is a digital signal applied serially to a serial input of the adjustable circuit.
14. The computing device as recited in claim 1 , wherein the reference frequency is generated in response to the clocking frequency applied to the critical path circuit.
15. A method of adjusting at least one of a supply voltage a power source and a clocking frequency applied to digital circuitry of a computing device, the digital circuitry comprising a critical path circuit, the method comprising the steps of:
(a) generating a propagation delay frequency representing a propagation delay of the critical path circuit;
(b) generating a reference frequency;
(c) generating a frequency error signal representing a difference between the reference frequency and the propagation delay frequency; and
(d) adjusting at least one of the supply voltage and the clocking frequency in response to the frequency error signal.
16. The method as recited in claim 15 , wherein the propagation delay frequency is generated using a matched delay oscillator.
17. The method as recited in claim 16 , further comprising the step of generating an integrated frequency error signal, wherein the step of adjusting at least one of the supply voltage and the clocking frequency is responsive to the integrated frequency error signal.
18. The method as recited in claim 17 , further comprising the steps of
(a) generating a proportional frequency error signal; and
(b) adding the integrated frequency error signal to the proportional frequency error signal to generate a proportional/integral frequency error signal, wherein the step of adjusting at least one of the supply voltage and the clocking frequency is responsive to the proportional/integral frequency error signal.
19. The method as recited in claim 17 , wherein the integrated frequency error signal is generated in discrete time.
20. The method as recited in claim 17 , wherein the integrated frequency error signal is a discrete-time signal.
21. The method as recited in claim 20 , further comprising the step of converting the integrated frequency error signal into an continuous-time signal, wherein the step of adjusting at least one of the supply voltage and the clocking frequency is responsive to the continuous-time signal.
22. The method as recited in claim 15 , the step of generating the frequency error signal comprises the steps of:
(a) clocking an up/down counter with the reference frequency for a first interval; and
(b) clocking the up/down counter with the propagation delay frequency for a second interval.
23. The method as recited in claim 22 , further comprising the step of programming at least one of the first and second intervals.
24. The method as recited in claim 22 , wherein the up/down counter outputs a pulse width modulated (PWM) signal having a duty cycle proportional to the difference between the reference frequency and the propagation delay frequency.
25. The method as recited in claim 24 , further comprising the step of filtering the PWM signal.
26. The method as recited in claim 15 , further comprising the step of transmitting the frequency error signal serially to an adjustable circuit for adjusting at least one of the supply voltage and clocking frequency.
27. The method as recited in claim 15 , further comprising the step of generating the reference frequency in response to the clocking frequency applied to the digital circuitry.