IP Library › Patent Application 10984701
Patent Application Utility
App. No. 10/984,701 · Confirmation No. 3859

Method for fabricating low leakage interconnect layers in integrated circuits

Abandoned -- Failure to Respond to an Office Action View Publication ↗
⬇ PDF
 Code Description Pages PDF
2007-03-07 ABN Abandonment 2 View
2006-08-04 IDS Information Disclosure Statement (IDS) Form (SB08) 3 View
2006-08-04 FOR Foreign Reference 9 View
2006-07-12 CTNF Non-Final Rejection 11 View
2006-07-12 EXIN Examiner Interview Summary Record (PTOL - 413) 1 View
2006-07-12 892 List of references cited by examiner 1 View
2006-07-12 FWCLM Index of Claims 1 View
2006-07-12 SRFW Search information including classification, databases and other search related notes 1 View
2006-07-09 SRNT Examiner's search strategy and results 4 View
2005-02-11 PEFR Applicant Response to Pre-Exam Formalities Notice 3 View
2005-02-11 OATH Oath or Declaration filed 2 View
2004-12-14 PEFN Pre-Exam Formalities Notice 2 View
2004-11-09 TRNA Transmittal of New Application 1 View
2004-11-09 SPEC Specification 22 View
2004-11-09 CLM Claims 8 View
2004-11-09 ABST Abstract 1 View
2004-11-09 DRW Drawings-only black and white line drawings 15 View
2004-11-09 OATH Oath or Declaration filed 2 View
2004-11-09 WFEE Fee Worksheet (SB06) 1 View
2004-11-09 WFEE Fee Worksheet (SB06) 1 View
2004-11-09 136A Authorization for Extension of Time all replies 1 View
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this application's details
Quick Facts
App. No.
10/984,701
Filed
2004-11-09
Pub. No.
US20060099800A1
Art Unit
2812