Cache memory system including a partially hashed index
View Patent ↗In one embodiment, a cache memory system includes a cache memory coupled to a cache controller. The cache memory controller may receive an address and generate an index value corresponding to the address for accessing a particular entry within the cache memory. More particularly, the cache controller may generate the index value by performing a hash function on a first portion of the address such as an address tag, and combining a result of the hash function with a second portion of the address such as an index, for example.
1. A cache memory system comprising:
a cache memory; and
a cache controller coupled to the cache memory, wherein the cache memory controller is configured to receive an address and to generate an index value corresponding to the address for accessing a particular entry within the cache memory;
wherein the cache controller is configured to generate the index value by performing a hash function on a first portion of the address and by combining a result of the hash function with a second portion of the address;
wherein performing the hash function includes performing a first bit-wise Exclusive-Or (XOR) operation on groups of selected bits of the first portion of the address; and
wherein the combining includes:
performing a second bit-wise Exclusive-Or operation between a first subset of bits of the second portion of the address and the result of the hash function; and
concatenating a second subset of the second portion with the result of the first bit-wise Exclusive-Or operation.
2. The cache system as recited in claim 1 , wherein the second portion of the address corresponds to an index including a number of address bits used to access a given size of the cache memory and the first portion of the address corresponds to an address tag including a number of most significant address bits not included in the index.
3. The cache system as recited in claim 2 , wherein the first portion of the address corresponds to all bits of the address tag.
4. The cache system as recited in claim 2 , wherein the cache controller is further configured to combine the result of the hash function with the first subset of the second portion of the address by performing a bit-wise Exclusive-Or operation between a selected subset of most significant bits of the index bits and the result of the hash function.
5. The cache system as recited in claim 4 , wherein the cache controller is further configured to access a particular section of the cache memory based upon any remaining least significant bits of the index that are not combined with the result of the hash function.
6. A method of accessing a cache memory, the method comprising:
receiving an address; and
generating an index value corresponding to the address for accessing a particular entry within the cache memory;
wherein generating an index value includes:
performing a hash function on a first portion of the address by performing a first bit-wise Exclusive-Or operation on groups of selected bits of the first portion of the address; and
combining a result of the hash function with a second portion of the address including:
performing a second bit-wise Exclusive-Or operation between a first subset of bits of the second portion of the address and the result of the hash function; and
concatenating a second subset of the second portion with the result of the first bit-wise Exclusive-Or operation.
7. The method as recited in claim 6 , wherein the second portion of the address corresponds to an index including a number of address bits used to access a given size of the cache memory and the first portion of the address corresponds to an address tag including a number of most significant address bits not included in the index.
8. The method as recited in claim 7 , wherein the first portion of the address corresponds to all bits of the address tag.
9. The method as recited in claim 7 , wherein combining the result of the hash function with the first subset of the second portion of the address includes performing a bit-wise Exclusive-Or operation between a selected subset of the most significant bits of the index bits and the result of the hash function.
10. The method as recited in claim 9 , further comprising accessing a particular section of the cache memory based upon any remaining least significant bits of the index that are not combined with the result of the hash function.
11. A computer system comprising:
a system memory;
a processor coupled to the system memory via a bus;
wherein the processor includes a cache memory system including:
a cache memory; and
a cache controller coupled to the cache memory, wherein the cache memory controller is configured to receive an address and to generate an index value corresponding to the address for accessing a particular entry within the cache memory;
wherein the cache controller is configured to generate the index value by performing a hash function on a first portion of the address and by combining a result of the hash function with a second portion of the address;
wherein performing the hash function includes performing a bit-wise Exclusive-Or (XOR) operation on groups of selected bits of the first portion of the address; and
wherein the combining includes:
performing a second bit-wise Exclusive-Or operation between a first subset of bits of the second portion of the address and the result of the hash function; and
concatenating a second subset of the second portion with the result of the first bit-wise Exclusive-Or operation.