Descrambler for descrambling scrambled data
A descrambler can speed up descrambling and prevent an increase in circuit scale. Received data is descrambled by an EXOR gate that receives a PN pattern signal output from a scramble pattern generator. The data is then converted to parallel data, and the CRC error correction is performed on the parallel data by a 1-bit error corrector. The 160-bit data, on which scrambling is performed is supplied to a parallel EXOR gate. When a PN pattern for descrambling scrambled data is generated by a user scramble pattern generator, the PN pattern output is converted to 160-bit parallel data, and is supplied to the parallel EXOR gate. The 160 EXOR gates descramble the input data bit by bit in parallel.
1 . A descrambler for descrambling scrambled parallel data, comprising:
a pattern generator for generating a descramble pattern for descrambling the parallel data;
a converter for converting the descramble pattern to a parallel form; and
an operation circuit connected to said converter for receiving the descramble pattern in the parallel form and the parallel data for performing a bit-by-bit exclusive OR operation.
2 . The descrambler in accordance with claim 1 , further comprising a corrector for performing error correction on a received signal in a parallel form and outputting the signal error-corrected as parallel data,
said operation circuit being connected to an output of said corrector for receiving the parallel data from said corrector.
3 . A descrambler for descrambling scrambled parallel data, comprising:
a pattern generator for holding a descramble pattern for descrambling the parallel data, receiving initial value data for descrambling as address data, and outputting data of the descramble pattern according to the initial value data in a parallel form; and
an operation circuit connected to said pattern generator for receiving the data of the descramble pattern and the parallel data for performing a bit-by-bit exclusive OR operation.
4 . The descrambler in accordance with claim 3 , further comprising:
a corrector for performing error correction on a received signal in a parallel form and outputting the signal error-corrected as parallel data,
said operation circuit being connected to an output of said corrector for receiving the parallel data from said corrector.