Method of manufacturing a semiconductor device that includes a process for forming a high breakdown voltage field effect transistor
View Patent ↗With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, n + type semiconductor regions, each having a conduction type opposite to p + type semiconductor regions for a source and drain of a high breakdown voltage pMIS, are disposed in a boundary region between each of trench type isolation portions at both ends, in a gate width direction, of a channel region of the high breakdown voltage pMIS and a semiconductor substrate at positions spaced away from p − type semiconductor regions, each having a field relaxing function, of the high breakdown voltage pMIS, so as not to contact the p − type semiconductor regions (on the drain side, in particular). The n + type semiconductor regions extend to positions deeper than the trench type isolation portions.
1. A method of manufacturing a semiconductor device, having a process for forming fifth and sixth high breakdown voltage field effect transistors in a semiconductor substrate, said method comprising the steps of:
(a) forming trench type isolation portions in a main surface of the semiconductor substrate and forming a plurality of active regions defined by the trench type isolation portions;
(b) forming a first conduction type seventh semiconductor region in the semiconductor substrate;
(c) forming an eighth semiconductor region of a second conduction type opposite to the first conduction type in the semiconductor substrate;
(d) forming source and drain ninth semiconductor regions of a second conduction type of the fifth high breakdown voltage field effect transistor in the seventh semiconductor region;
(e) forming source and drain tenth semiconductor regions of a first conduction type of the sixth high breakdown voltage field effect transistor in the eighth semiconductor region;
(f) forming a gate insulating film over the semiconductor substrate;
(g) forming a gate electrode over the gate insulating film;
(h) forming, in the ninth semiconductor regions, source and drain eleventh semiconductor regions of a second conduction type of the fifth high breakdown voltage field effect transistor, which are semiconductor regions higher in impurity concentration than the ninth semiconductor regions; and
(i) forming, in the tenth semiconductor regions, source and drain twelfth semiconductor regions of a first conduction type of the sixth high breakdown voltage field effect transistor, which are semiconductor regions higher in impurity concentration than the tenth semiconductor regions,
wherein the source and drain second conduction type eleventh semiconductor regions of the fifth high breakdown voltage field effect transistor are formed in their corresponding active regions disposed via the trench type isolation portions on both sides in a gate length direction, of the active region in which a channel region of the fifth high breakdown voltage field effect transistor is disposed,
wherein the source and drain second conduction type ninth semiconductor regions of the fifth high breakdown voltage field effect transistor are formed so as to electrically connect the source and drain second conduction type eleventh semiconductor regions with the channel region of the fifth high breakdown voltage field effect transistor,
wherein the source and drain first conduction type twelfth semiconductor regions of the sixth high breakdown voltage field effect transistor are formed in their corresponding active regions disposed via the trench type isolation portions on both sides in a gate length direction, of the active region in which a channel region of the sixth high breakdown voltage field effect transistor is disposed,
wherein the source and drain first conduction type tenth semiconductor regions of the sixth high breakdown voltage field effect transistor are formed so as to electrically connect the source and drain first conduction type twelfth semiconductor regions with the channel region of the sixth high breakdown voltage field effect transistor,
wherein when the source and drain second conduction type ninth semiconductor regions of the fifth high breakdown voltage field effect transistor are formed, a second conduction type thirteenth semiconductor region higher in impurity concentration than the eighth semiconductor region is formed in a boundary region between the corresponding trench type isolation portion at both ends in a gate width direction, of the sixth high breakdown voltage field effect transistor and the semiconductor substrate so as not to contact the source and drain first conduction type tenth and twelfth semiconductor regions of the sixth high breakdown voltage field effect transistor and so as to be spaced away from the tenth and twelfth semiconductor regions, and
wherein when the source and drain first conduction type tenth semiconductor regions of the sixth high breakdown voltage field effect transistor are formed, a first conduction type fourteenth semiconductor region higher in impurity concentration than the seventh semiconductor region is formed in a boundary region between the corresponding trench type isolation portion at both ends in a gate width direction, of the fifth high breakdown voltage field effect transistor and the semiconductor substrate so as not to contact the source and drain second conduction type ninth and eleventh semiconductor regions of the fifth high breakdown voltage field effect transistor and so as to be spaced away from the ninth and eleventh semiconductor regions.
2. A method of manufacturing a semiconductor device, having a process for forming seventh and eighth high breakdown voltage field effect transistors in a semiconductor substrate, said method comprising the steps of:
(a) forming trench type isolation portions in a main surface of the semiconductor substrate and forming a plurality of active regions defined by the trench type isolation portions;
(b) forming a first conduction type seventh semiconductor region in the semiconductor substrate;
(c) forming an eighth semiconductor region of a second conduction type opposite to the first conduction type in the semiconductor substrate;
(d) forming a drain ninth semiconductor region of a second conduction type of the seventh high breakdown voltage field effect transistor in the seventh semiconductor region;
(e) forming a drain tenth semiconductor region of a first conduction type of the eighth high breakdown voltage field effect transistor in the eighth semiconductor region;
(f) forming a gate insulating film over the semiconductor substrate;
(g) forming a gate electrode over the gate insulating film;
(h) forming, in the ninth semiconductor region, a drain eleventh semiconductor region of a second conduction type of the seventh high breakdown voltage field effect transistor, which is a semiconductor region higher in impurity concentration than the ninth semiconductor region, and forming, in the seventh semiconductor region, a source eleventh semiconductor region of a second conduction type of the seventh high breakdown voltage field effect transistor, which is a semiconductor region higher in impurity concentration than the ninth semiconductor region; and
(i) forming, in the tenth semiconductor region, a drain twelfth semiconductor region of a first conduction type of the eighth high breakdown voltage field effect transistor, which is a semiconductor region higher in impurity concentration than the tenth semiconductor region, and forming, in the eighth semiconductor region, a source twelfth semiconductor region of a first conduction type of the eighth high breakdown voltage field effect transistor, which is a semiconductor region higher in impurity concentration than the tenth semiconductor region,
wherein the drain second conduction type eleventh semiconductor region of the seventh high breakdown voltage field effect transistor is formed in the corresponding active region disposed via the corresponding trench type isolation portion on one side in a gate length direction, of the active region in which a channel region of the seventh high breakdown voltage field effect transistor is disposed,
wherein the source second conduction type eleventh semiconductor region of the seventh high breakdown voltage field effect transistor is formed without via the trench type isolation portion in a state of being adjacent to the other side in the gate length direction, of the active region in which the channel region of the seventh high breakdown voltage field effect transistor is disposed,
wherein the drain second conduction type ninth semiconductor region of the seventh high breakdown voltage field effect transistor is formed so as to electrically connect the drain second conduction type eleventh semiconductor region with the channel region of the seventh high breakdown voltage field effect transistor,
wherein the drain first conduction type twelfth semiconductor region of the eighth high breakdown voltage field effect transistor is formed in the corresponding active region disposed via the corresponding trench type isolation portion on one side in a gate length direction, of the active region in which a channel region of the eighth high breakdown voltage field effect transistor is disposed,
wherein the source first conduction type twelfth semiconductor region of the eighth high breakdown voltage field effect transistor is formed without via the trench type isolation portion in a state of being adjacent to the other side in the gate length direction, of the active region in which the channel region of the eighth high breakdown voltage field effect transistor is disposed,
wherein the drain first conduction type tenth semiconductor region of the eighth high breakdown voltage field effect transistor is formed so as to electrically connect the drain first conduction type twelfth semiconductor region with the channel region of the eighth high breakdown voltage field effect transistor,
wherein when the drain second conduction type ninth semiconductor region of the seventh high breakdown voltage field effect transistor is formed, a second conduction type thirteenth semiconductor region higher in impurity concentration than the eighth semiconductor region is formed in a boundary region between the corresponding trench type isolation portion at both ends in a gate width direction, of the eighth high breakdown voltage field effect transistor and the semiconductor substrate so as not to contact the drain first conduction type tenth and twelfth semiconductor regions of the eighth high breakdown voltage field effect transistor and so as to be spaced away from the tenth and twelfth semiconductor regions, and
wherein when the drain first conduction type tenth semiconductor region of the eighth high breakdown voltage field effect transistor is formed, a first conduction type fourteenth semiconductor region higher in impurity concentration than the seventh semiconductor region is formed in a boundary region between the corresponding trench type isolation portion at both ends in a gate width direction, of the seventh high breakdown voltage field effect transistor and the semiconductor substrate so as not to contact the drain second conduction type ninth and eleventh semiconductor regions of the seventh high breakdown voltage field effect transistor and so as to be spaced away from the ninth and eleventh semiconductor regions.
3. A method of manufacturing a semiconductor device, having a process for forming seventh and eighth high breakdown voltage field effect transistors in a semiconductor substrate, said method comprising the steps of:
(a) forming trench type isolation portions in a main surface of the semiconductor substrate and forming a plurality of active regions defined by the trench type isolation portions;
(b) forming a first conduction type seventh semiconductor region in the semiconductor substrate;
(c) forming an eighth semiconductor region of a second conduction type opposite to the first conduction type in the semiconductor substrate;
(d) forming a drain ninth semiconductor region of a second conduction type of the seventh high breakdown voltage field effect transistor in the seventh semiconductor region;
(e) forming a drain tenth semiconductor region of a first conduction type of the eighth high breakdown voltage field effect transistor in the eighth semiconductor region;
(f) forming a gate insulating film for the seventh and eighth high breakdown voltage field effect transistors over the semiconductor substrate;
(g) forming gate electrodes for the seventh and eighth high breakdown voltage field effect transistors over the gate insulating film;
(h) forming, in the ninth semiconductor region, a drain eleventh semiconductor region of a second conduction type of the seventh high breakdown voltage field effect transistor, which is a semiconductor region higher in impurity concentration than the ninth semiconductor region, and forming, in the seventh semiconductor region, a source eleventh semiconductor region of a second conduction type of the seventh high breakdown voltage field effect transistor, which is a semiconductor region higher in impurity concentration than the ninth semiconductor region;
(i) forming, in the tenth semiconductor region, a drain twelfth semiconductor region of a first conduction type of the eighth high breakdown voltage field effect transistor, which is a semiconductor region higher in impurity concentration than the tenth semiconductor region, and forming, in the eighth semiconductor region, a source twelfth semiconductor region of a first conduction type of the eighth high breakdown voltage field effect transistor, which is a semiconductor region higher in impurity concentration than the tenth semiconductor region;
(j) forming a gate insulating film for a low breakdown voltage field effect transistor;
(k) forming a gate electrode for the low breakdown voltage field effect transistor; and
(l) forming source and drain fifteenth semiconductor regions for the low breakdown voltage field effect transistor,
wherein the drain second conduction type eleventh semiconductor region of the seventh high breakdown voltage field effect transistor is formed in the corresponding active region disposed via the corresponding trench type isolation portion on one side in a gate length direction, of the active region in which a channel region of the seventh high breakdown voltage field effect transistor is disposed,
wherein the source second conduction type eleventh semiconductor region of the seventh high breakdown voltage field effect transistor is formed without via the trench type isolation portion in a state of being adjacent to the other side in the gate length direction, of the active region in which the channel region of the seventh high breakdown voltage field effect transistor is disposed,
wherein the drain second conduction type ninth semiconductor region of the seventh high breakdown voltage field effect transistor is formed so as to electrically connect the drain second conduction type eleventh semiconductor region with the channel region of the seventh high breakdown voltage field effect transistor,
wherein the drain first conduction type twelfth semiconductor region of the eighth high breakdown voltage field effect transistor is formed in the corresponding active region disposed via the corresponding trench type isolation portion on one side in a gate length direction, of the active region in which a channel region of the eighth high breakdown voltage field effect transistor is disposed,
wherein the source first conduction type twelfth semiconductor region of the eighth high breakdown voltage field effect transistor is formed without via the trench type isolation portion in a state of being adjacent to the other side in the gate length direction, of the active region in which the channel region of the eighth high breakdown voltage field effect transistor is disposed,
wherein the drain first conduction type tenth semiconductor region of the eighth high breakdown voltage field effect transistor is formed so as to electrically connect the drain first conduction type twelfth semiconductor region with the channel region of the eighth high breakdown voltage field effect transistor,
wherein when the drain second conduction type ninth semiconductor region of the seventh high breakdown voltage field effect transistor is formed, a second conduction type thirteenth semiconductor region higher in impurity concentration than the eighth semiconductor region is formed in a boundary region between the corresponding trench type isolation portion at both ends in a gate width direction, of the eighth high breakdown voltage field effect transistor and the semiconductor substrate so as not to contact the drain first conduction type tenth and twelfth semiconductor regions of the eighth high breakdown voltage field effect transistor and so as to be spaced away from the tenth and twelfth semiconductor regions,
wherein when the drain first conduction type tenth semiconductor region of the eighth high breakdown voltage field effect transistor is formed, a first conduction type fourteenth semiconductor region higher in impurity concentration than the seventh semiconductor region is formed in a boundary region between the corresponding trench type isolation portion at both ends in a gate width direction, of the seventh high breakdown voltage field effect transistor and the semiconductor substrate so as not to contact the drain second conduction type ninth and eleventh semiconductor regions of the seventh high breakdown voltage field effect transistor and so as to be spaced away from the ninth and eleventh semiconductor regions, and
wherein after the formation of the gate electrode of the low breakdown voltage field effect transistor, the gate electrodes of the seventh and eighth high breakdown voltage field effect transistors are formed.
4. The method according to claim 1 , 2 or 3 , wherein the thirteenth and fourteenth semiconductor regions are formed so as to extend to positions deeper than the isolation portions from the main surface of the semiconductor substrate.
5. A method of manufacturing a semiconductor device, having a process for forming a high breakdown voltage field effect transistor and a low breakdown voltage field effect transistor lower in operating voltage than the high breakdown voltage field effect transistor in a semiconductor substrate, said method comprising the steps of:
(a) forming trench type isolation portions in a main surface of the semiconductor substrate and forming a plurality of active regions defined by the trench type isolation portions;
(b) forming a first conduction type seventh semiconductor region in the semiconductor substrate;
(c) forming, in the seventh semiconductor region, a drain ninth semiconductor region of a second conduction type of the high breakdown voltage field effect transistor, which is a semiconductor region of a second conduction type opposite to the first conduction type;
(d) forming a first conduction type fourteenth semiconductor region higher in impurity concentration than the seventh semiconductor region in a boundary region between the corresponding trench type isolation portion at both ends in a gate width direction, of the high breakdown voltage field effect transistor and the semiconductor substrate so as not to contact the drain second conduction type ninth semiconductor region of the high breakdown voltage field effect transistor and so as to be spaced away from the ninth semiconductor region;
(e) forming a gate insulating film for the high breakdown voltage field effect transistor over the semiconductor substrate;
(f) forming a gate electrode for the high breakdown voltage field effect transistor over the gate insulating film for the high breakdown voltage field effect transistor;
(g) forming, in the ninth semiconductor region, a drain eleventh semiconductor region of a second conduction type of the high breakdown voltage field effect transistor, which is a semiconductor region higher in impurity concentration than the ninth semiconductor region, and forming, in the seventh semiconductor region, a source eleventh semiconductor region of a second conduction type of the high breakdown voltage field effect transistor, which is a semiconductor region higher in impurity concentration than the ninth semiconductor region;
(h) forming a gate insulating film for the low breakdown voltage field effect transistor;
(i) forming a gate electrode for the low breakdown voltage field effect transistor; and
(j) forming source and drain fifteenth semiconductor regions for the low breakdown voltage field effect transistor,
wherein the drain second conduction type eleventh semiconductor region of the high breakdown voltage field effect transistor is formed in the corresponding active region disposed via the corresponding trench type isolation portion on one side in a gate length direction, of the active region in which a channel region of the high breakdown voltage field effect transistor is disposed,
wherein the source second conduction type eleventh semiconductor region of the high breakdown voltage field effect transistor is formed without via the trench type isolation portion in a state of being adjacent to the other side in the gate length direction, of the active region in which the channel region of the high breakdown voltage field effect transistor is disposed,
wherein the drain second conduction type ninth semiconductor region of the high breakdown voltage field effect transistor is formed so as to electrically connect the drain second conduction type eleventh semiconductor region with the channel region of the high breakdown voltage field effect transistor, and
wherein after the formation of the gate electrode of the low breakdown voltage field effect transistor, the gate electrode of the high breakdown voltage field effect transistor is formed.
6. The method according to claim 5 , wherein the fourteenth semiconductor region is formed so as to extend to a position deeper than the isolation portions from the main surface of the semiconductor substrate.