Ultra-wideband communication apparatus and methods
View Patent ↗Apparatus and methods of ultra-wideband (UWB) communication are provided. In one embodiment, an ultra-wideband transmitter includes a processor configured to generate data for transmission in the form of a plurality of ultra-wideband pulses. The transmitter includes a FEC encoder that generates a code word based on the data. The FEC includes a plurality of cyclic shift registers configured to receive and process the data, a plurality of fixed connections between each of the plurality of cyclic shift registers and a plurality of XOR gates communicating with the plurality of fixed connections. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the subject matter of the disclosure contained herein. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.
1. An ultra-wideband transmitter, comprising:
a processor configured to generate data to be transmitted in the form of a plurality of ultra-wideband pulses by the transmitter, and
a forward error correction encoder configured to generate a code word based on the data, the forward error correction encoder comprising:
a plurality of cyclic shift registers configured to receive and process the data;
a plurality of fixed connections between each of the plurality of cyclic shift registers,
a plurality of XOR gates communicating with the plurality of fixed connections, the fixed connections arranged such that the first fixed connection communicates with the first of the plurality of XOR gates, the second fixed connection communicates with the second of the plurality of XOR gates, and so on until the last of the fixed connections communicates with the last of the plurality of XOR gates;
further comprising a register configured to store an output of each of the plurality of XOR gates; and;
further comprising a register XOR gate communicating with the register, the register XOR gate configured to XOR an output of the register with a delayed version of the output of the register.
2. An ultra-wideband transmitter, comprising:
a processor configured to generate data to be transmitted in the form of a plurality of ultra-wideband pulses by the transmitter, and
a forward error correction encoder configured to generate a code word based on the data, the forward error correction encoder comprising:
a plurality of cyclic shift registers configured to receive and process the data;
a plurality of fixed connections between each of the plurality of cyclic shift registers,
a plurality of XOR gates communicating with the plurality of fixed connections, the fixed connections arranged such that the first fixed connection communicates with the first of the plurality of XOR gates, the second fixed connection communicates with the second of the plurality of XOR gates, and so on until the last of the fixed connections communicates with the last of the plurality of XOR gates;
wherein the code word is generated using a parity matrix, and the parity matrix comprises a matrix of cyclic matrices; and
wherein a first of the cyclic matrices is generated from an identity matrix and a permutation vector, and each of the subsequent cyclic matrices are generated by rotating the previous cyclic matrix.
3. An ultra-wideband transmitter, comprising:
a processor configured to generate data to be transmitted in the form of a plurality of ultra-wideband pulses by the transmitter, and
a forward error correction encoder configured to generate a code word based on the data, the forward error correction encoder comprising:
a plurality of cyclic shift registers configured to receive and process the data;
a plurality of fixed connections between each of the plurality of cyclic shift registers,
a plurality of XOR gates communicating with the plurality of fixed connections, the fixed connections arranged such that the first fixed connection communicates with the first of the plurality of XOR gates, the second fixed connection communicates with the second of the plurality of XOR gates, and so on until the last of the fixed connections communicates with the last of the plurality of XOR gates;
wherein the plurality of fixed connections are arranged based on a dual diagonal matrix and a cyclic matrix.