Driver circuit
View Patent ↗A driver circuit for driving a load ( 3 ) connected between an output (FO) of a first channel driver (D 1 ) and an output (RO) of a second channel driver (D 2 ). The first and second channel drivers (D 1 , D 2 ) each include switch transistors for charging and discharging the gates of upper and lower output transistors in response to a command from an input pulse, a charging/discharging circuit (A 2 , B 2 ) for determining a charging/discharging speed, and a detector circuit (A 1 , B 1 ) for detecting a state of the channel driver on the opposite side. A dead time period and a speed of charging/discharging the gates of the upper and lower output transistors are changed according to the state of the channel driver on the opposite side. Thus, it is possible to achieve a channel driver circuit which can prevent a shoot-through current, adjust an output slew rate, and obtain preferred linearity as an input-output characteristic.
1. A driver circuit for driving a load connected between an output of a first channel driver and an output of a second channel driver,
the first and second channel drivers each comprising:
a charging/discharging circuit comprising a switch transistor for charging and discharging each gate of upper and lower output transistors in response to a command from an input pulse, and a circuit for determining a charging/discharging speed for each gate; and
a detector circuit for detecting a state of the channel driver on an opposite side,
wherein a change is made to a dead time period and the speed of charging/discharging the gates of the upper and lower output transistors, according to the state of the channel driver on the opposite side,
wherein
the detector circuit detects a level of the input pulse on the opposite side,
when the input pulse on the opposite side is set at “H”, dead time is provided only at a rising edge of an input, the gate of the lower output transistor is discharged at a lower speed, and the gate of the upper output transistor is discharged at a higher speed, and
when the input pulse on the opposite side is set at “L”, the dead time is provided only at a falling edge of the input, the gate of the upper output transistor is discharged at a lower speed, and the gate of the lower output transistor is discharged at a higher speed.
2. The driver circuit according to claim 1 , wherein
the detector circuit detects a level of an output pulse on the opposite side,
when the output pulse on the opposite side is set at “H”, dead time is provided only at a rising edge of an input, the gate of the lower output transistor is discharged at a lower speed, and the gate of the upper output transistor is discharged at a higher speed, and
when the output pulse on the opposite side is set at “L”, the dead time is provided only at a falling edge of the input (output), the gate of the upper output transistor is discharged at a lower speed, and the gate of the lower output transistor is discharged at a higher speed.
3. The driver circuit according to claim 1 , wherein
the detector circuit detects a level of a voltage between the gate and source of each of the upper and lower output transistors on the opposite side,
when the voltage between the gate and source of the upper output transistor is set at “H”, dead time is provided only at a rising edge of the input pulse, the gate of the lower output transistor is discharged at a lower speed, and the gate of the upper output transistor is discharged at a higher speed, and
when a voltage between the gate and source of the lower output transistor is set at “H”, the dead time is provided only at a falling edge of the input pulse, the gate of the upper output transistor is discharged at a lower speed, and the gate of the lower output transistor is discharged at a higher speed.
4. The driver circuit according to claim 1 , wherein it is detected that the input pulse or the output pulse has a duty close to 50% on both sides, no dead time is provided for a driving pulse for charging and discharging the output transistors on both sides, and the gates of the upper and lower output transistors on both sides are discharged at a higher speed.
5. A driver circuit for driving a load connected between an output of a first channel driver and an output of a second channel driver,
the first and second channel drivers each comprising:
a charging/discharging circuit comprising a switch transistor for charging and discharging each gate of upper and lower output transistors in response to a command from an input pulse, and a circuit for determining a charging/discharging speed for each gate; and
a detector circuit for detecting a current passing through the upper and lower output transistors of its own channel driver, wherein a change is made to a dead time period and the speed of charging/discharging the gates of the upper and lower output transistors, according to a state of the current passing through the upper and lower output transistors,
wherein when the detector circuit detects that a current of not lower than a specified value passes through the lower output transistor, dead time is provided at a rising edge of the input pulse, and the gate of the lower output transistor is discharged at a lower speed,
when the detector circuit detects that a current of not lower than the specified value does not pass through the lower output transistor, no dead time is provided at the rising edge of the input pulse, and the gate of the lower output transistor is discharged at a higher speed,
when the detector circuit detects that a current of not lower than the specified value passes through the upper output transistor, the dead time is provided at a falling edge of the input pulse, and the gate of the upper output transistor is discharged at a lower speed, and
when the detector circuit detects that a current of not lower than the specified value does not pass through the upper output transistor, no dead time is provided at the falling edge of the input pulse, and the gate of the upper output transistor is discharged at a higher speed.
6. The driver circuit according to claim 5 , wherein the detector circuit comprises a comparator for comparing an output voltage with a certain voltage, and makes a comparison between a threshold current and an output current calculated according to a logic that an output voltage is determined by a product of an on-resistance of an output transistor and an output current.