IP Library Granted Patent US 7,166,902
Granted Patent B1
US 7,166,902 · App. 10/988,812 · Granted Jan 23, 2007

Trench-based capacitor for integrated circuits

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Quick Facts
Patent No.
US 7,166,902
App. No.
10/988,812
Granted
Jan 23, 2007
Kind
B1
Abstract

In one embodiment, an electrically conductive trench in an integrated circuit allows for the formation of capacitors between the trench and other portions of the integrated circuit. For example, a capacitor may be formed between the trench and an electrically conductive line. Among other advantages, the capacitor provides a relatively large capacitance while occupying a relatively small area.

Claims (14)

1. An integrated circuit structure comprising:

a plurality of electrically conductive lines over a substrate;

a plurality of electrically conductive trenches over the plurality of electrically conductive lines, each of the plurality of electrically conductive trenches spanning and filling a space between at least two electrically conductive lines in the plurality of electrically conductive lines; and

a capacitor designed for use as a component of an electrical circuit, the capacitor formed using at least a first electrically conductive trench in the plurality of electrically conductive trenches.

2. The integrated circuit structure of claim 1 wherein the capacitor is formed by the first electrically conductive trench, a sidewall of a first electrically conductive line in the plurality of electrically conductive lines, and a dielectric between the first electrically conductive trench and the sidewall of the first electrically conductive line.

3. The integrated circuit structure of claim 1 wherein the capacitor is formed by the first electrically conductive trench, a top portion of a first electrically conductive line in the plurality of electrically conductive lines, and a dielectric between the first electrically conductive trench and the top portion of the first electrically conductive line.

4. The integrated circuit structure of claim 1 wherein the capacitor is formed by the first electrically conductive trench, a second electrically conductive trench in the plurality of electrically conductive trenches, and a dielectric between the first electrically conductive trench and the second electrically conductive trench.

5. The integrated circuit structure of claim 1 wherein the plurality of electrically conductive trenches is across the plurality of electrically conductive lines.

6. The integrated circuit structure of claim 1 wherein the electrically conductive trenches comprise tungsten.

7. The integrated circuit structure of claim 1 further comprising spacers formed on sidewalls of the electrically conductive lines.

8. The integrated circuit structure of claim 1 further comprising:

a plurality of local interconnect lines formed over and across the plurality of electrically conductive trenches.

9. The integrated circuit structure of claim 8 wherein the capacitor is formed by a first local interconnect line in the plurality of local interconnect lines, the first electrically conductive trench, and a dielectric between the first local interconnect line and the first electrically conductive trench.

10. The integrated circuit structure of claim 8 further comprising a plurality of first level interconnect lines formed over and across the plurality of local interconnect lines.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 26, 2014
From: CYPRESS SEMICONDUCTOR CORPORATION
To: DECA TECHNOLOGIES, INC.
Reel/Frame 032534/0431 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 15, 2004
From: BADRIEH, FUAD; DAI, FENG; BANACHOWICZ, BARTOSZ; BETTMAN, ROGER J.
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 016001/0244 →