Integrated circuit with improved RC delay
View Patent ↗In one embodiment, a passivation level includes a low-k dielectric. The low-k dielectric helps lower the capacitance of a metal line in a last metal level, which may be just below the passivation level. In another embodiment, the metal line is relatively thick. This helps lower the metal line's resistance and resulting RC delay.
1. A method of fabricating an integrated circuit, the method comprising:
forming metal lines in a last metal level;
forming a low-k dielectric layer over and between a first metal line and a second metal line, the low-k dielectric layer substantially filing a space extending between sidewalls of the first and second metal lines, the first and second metal lines being in the last metal level; and
forming a passivation level over the last metal level such that the low-k dielectric layer remains over and between the first and second metal lines.
2. The method of claim 1 wherein the low-k dielectric layer has a dielectric constant less than about 3.9.
3. The method of claim 1 wherein the metal lines are formed over a dielectric level comprising a dielectric material having a dielectric constant less than about 3.9.
4. The method of claim 1 wherein the metal lines comprise aluminum.
5. The method of claim 1 wherein the low-k dielectric layer comprises a low-k dielectric material having gap-fill capability.
6. The method of claim 1 wherein the passivation level includes the low-k dielectric layer and a topside layer over the low-k dielectric layer.
7. The method of claim 1 wherein forming the passivation level comprises:
forming a topside layer over the low-k dielectric layer.
8. The method of claim 1 wherein forming the passivation level comprises:
forming a capping layer over the low-k dielectric layer; and
forming a topside layer over the capping layer.
9. The method of claim 8 wherein the capping layer comprises silicon dioxide.
10. The method of claim 8 wherein the topside layer comprises silicon nitride.
11. A method of fabricating an integrated circuit, the method comprising:
forming metal lines in a last metal level; and
forming a passivation level over the metal lines, the passivation level comprising a low-k dielectric substantially filling a space between sidewalls of the metal lines, the low-k dielectric being over the metal lines.
12. The method of claim 11 wherein the passivation level further comprises a capping material over the low-k dielectric.
13. The method of claim 12 wherein the capping material comprises silicon dioxide.
14. The method of claim 11 wherein the passivation level comprises a topside material over the low-k dielectric.
15. The method of claim 14 wherein the topside material comprises silicon nitride.
16. The method of claim 11 wherein the low-k dielectric has gap-fill capability.
17. The method of claim 11 wherein the low-k dielectric has a dielectric constant less than about 3.9.
18. A method of fabricating an integrated circuit, the method comprising:
forming a last metal level over a dielectric layer; and
forming a low-k dielectric layer over and between metal lines in the last metal level, the low-k dielectric layer being formed directly on the dielectric layer.
19. The method of claim 18 wherein the low-k dielectric layer has a dielectric constant less than about 3.9.
20. The method of claim 18 wherein the low-k dielectric layer has gap-fill capability.