Method of manufacturing multiple-gate MOS transistor having an improved channel structure
View Patent ↗Provided is a multiple-gate metal oxide semiconductor (MOS) transistor and a method for manufacturing the same, in which a channel is implemented in a streamline shape, an expansion region is implemented in a gradually increased form, and source and drain regions is implemented in an elevated structure by using a difference of a thermal oxidation rate depending on a crystal orientation of silicon and a geographical shape of the single-crystal silicon pattern. As the channel is formed in a streamline shape, it is possible to prevent the degradation of reliability due to concentration of an electric field and current driving capability by the gate voltage is improved because the upper portion and both sides of the channel are surrounded by the gate electrodes. In addition, a current crowding effect is prevented due to the expansion region increased in size and source and drain series resistance is reduced by elevated source and drain structures, thereby increasing the current driving capability.
1. A method of manufacturing a multiple-gate metal oxide semiconductor (MOS) transistor, the method comprising:
forming a single-crystal silicon pattern on an insulating layer the single-crystal silicon pattern providing source and drain regions, a channel region formed between the source and drain regions, and expansion regions interconnecting the source and drain regions, respectively, with the channel region;
forming a silicon oxide layer and a nitride layer on the single-crystal silicon pattern;
patterning the nitride layer to expose a top surface of the silicon oxide layer that exists in parts of the channel region and the expansion regions;
forming an oxide layer taking a form of a field oxide layer having a beak in the channel region and the expansion regions by subjecting the exposed portion of the top surface of the silicon oxide layer to oxidation;
using the patterned nitride layer as a mask removing the formed oxide layer of the channel region and the expansion regions to expose the single-crystal silicon pattern of the channel region and expansion regions;
forming a gate insulating layer on an exposed single-crystal silicon pattern of the channel region;
forming a gate electrode on the gate insulating layer; and
implanting impurity ions into the single-crystal silicon pattern of the source and drain regions.
2. The method as recited in claim 1 , wherein forming the silicon oxide layer and the nitride layer on the single-crystal silicon pattern comprising forming the silicon oxide layer with different thicknesses on an upper portion and both sides of the single-crystal silicon pattern.
3. The method as recited in claim 1 , wherein the oxide layer taking the form of the field oxide layer is formed by a thermal oxidation process.
4. The method as recited in claim 3 , wherein the thermal oxidation process is carried out by a wet oxidation method or wet and dry oxidation methods.
5. The method as recited in claim 1 , wherein the single-crystal silicon pattern of the channel region has an upper portion formed in a streamline shape and has a size gradually increased toward the source and drain regions by forming the oxide layer.
6. The method as recited in claim 5 , wherein the streamline shape is formed by a difference of a thermal oxidation rate depending on a crystal orientation of the single-crystal silicon.
7. The method as recited in claim 1 , wherein the oxide layer is removed by a dry etching method.
8. The method as recited in claim 1 , further comprising forming insulating layer spacers on sidewalls of the nitride layer before forming the gate insulating layer.
9. The method as recited in claim 1 , wherein the oxide layer is removed by a wet etching method.