High speed binary counter
View Patent ↗A high speed binary counter includes a counting first flip-flop for each binary bit, a single AND gate for each lower order binary bit beyond B 0 and B 1 , and at least two AND gates for each higher order binary bit. The counter also includes an input factor delay second flip-flop. The counter is further provided with a mechanism for redundant least significant terms for lesser order bits.
1. A high speed binary counter, comprising:
a counting first flip-flop for each binary bit;
a single AND gate for each lower order binary bit beyond B 0 and B 1 ;
at least two AND gates for each higher order binary bit; and
further including an input factor delay second flip-flop wherein each first flip-flop is a toggle flip-flop and each second flip-flop is a D-flip-flop.
2. The high speed binary counter according to claim 1 , wherein each first flip-flop is a D flip-flop.
3. The high speed binary counter according to claim 1 , wherein the lower order binary bits beyond B 0 and B 1 are B 2 , B 3 and B 4 .
4. The high speed binary counter according to claim 3 , wherein the higher order binary bits are B 5 and above.
5. The high speed binary counter according to claim 1 , wherein the higher order binary bits are B 5 and above.
6. The high speed binary counter according to claim 1 , further including means for redundant least significant terms for lesser order bits.
7. The high speed binary counter according to claim 6 , wherein the means for redundant least significant terms includes replication of term B 0 for all counter terms of the binary counter.
8. The high speed binary counter according to claim 6 , wherein the means for redundant least significant terms includes replication of term B 1 for all counter terms of the binary counter.
9. A high speed binary counter, comprising:
a counting first flip-flop for each binary bit;
a single AND gate for each lower order binary bit beyond B 0 and B 1 ; and
a means for partial input factor delay for each higher order binary bit;
wherein the means for partial input factor delay is a second AND gate applied to each higher order binary bit and an input factor delay second flip-flop.
10. The high speed binary counter according to claim 9 , wherein each first flip-flop is a D flip-flop.
11. The high speed binary counter according to claim 10 , wherein second flip-flop is a D flip-flop.
12. The high speed binary counter according to claim 9 , wherein each first flip-flop is a toggle flip-flop.
13. The high speed binary counter according to claim 12 , wherein second flip-flop is a D flip-flop.
14. The high speed binary counter according to claim 9 , wherein the lower order binary bits are B 2 , B 3 and B 4 .
15. The high speed binary counter according to claim 14 , wherein the higher order binary bits are B 5 and above.
16. The high speed binary counter according to claim 9 , wherein the higher order binary bits are B 5 and above.
17. The high speed binary counter according to claim 9 , further including means for redundant least significant terms for lesser order bits.
18. The high speed binary counter according to claim 17 , wherein the means for redundant least significant terms includes replication of term B 0 for all counter terms of the binary counter.
19. The high speed binary counter according to claim 9 , wherein each first flip-flop is a D flip-flop.
20. A high speed binary counter, comprising:
a counting first flip-flop for each binary bit;
a single AND gate for each lower order binary bit beyond B 0 and B 1 ;
at least two AND gates for each higher order binary bit; and
further including means for redundant least significant terms for lesser order bits.
21. The high speed binary counter according to claim 20 , wherein each first flip-flop is a toggle flip-flop.
22. The high speed binary counter according to claim 20 , wherein the lower order binary bits beyond B 0 and B 1 are B 2 , B 3 and B 4 .
23. The high speed binary counter according to claim 22 , wherein the higher order binary bits are B 5 and above.
24. The high speed binary counter according to claim 20 , wherein the higher order binary bits are B 5 and above.
25. The high speed binary counter according to claim 20 , wherein the means for redundant least significant terms includes replication of term B 0 for all counter terms of the binary counter.
26. The high speed binary counter according to claim 20 , wherein the means for redundant least significant terms includes replication of term B 1 for all counter terms of the binary counter.
27. A high speed binary counter, comprising:
a counting first flip-flop for each binary bit;
a single AND gate for each lower order binary bit beyond B 0 and B 1 ; and
a means for partial input factor delay for each higher order binary bit;
wherein each first flip-flop is a D flip-flop and wherein the means for partial input factor delay is a second AND gate applied to each higher order binary bit and a second flip-flop which is a D flip-flop.
28. The high speed binary counter according to claim 27 , wherein the lower order binary bits are B 2 , B 3 and B 4 .
29. The high speed binary counter according to claim 28 , wherein the higher order binary bits are B 5 and above.
30. The high speed binary counter according to claim 27 , wherein the higher order binary bits are B 5 and above.
31. The high speed binary counter according to claim 27 , further including means for redundant least significant terms for lesser order bits.
32. The high speed binary counter according to claim 31 , wherein the means for redundant least significant terms includes replication of term B 0 for all counter terms of the binary counter.
33. A high speed binary counter, comprising:
a counting first flip-flop for each binary bit;
a single AND gate for each lower order binary bit beyond B 0 and B 1 ; and
a means for partial input factor delay for each higher order binary bit;
wherein each first flip-flop is a toggle flip-flop and wherein the means for partial input factor delay is a second AND gate applied to each higher order binary bit and a second flip-flop which is a D flip-flop.
34. The high speed binary counter according to claim 33 , wherein the lower order binary bits are B 2 , B 3 and B 4 .
35. The high speed binary counter according to claim 34 , wherein the higher order binary bits are B 5 and above.
36. The high speed binary counter according to claim 33 , wherein the higher order binary bits are B 5 and above.
37. The high speed binary counter according to claim 33 , further including means for redundant least significant terms for lesser order bits.
38. The high speed binary counter according to claim 37 , wherein the means for redundant least significant terms includes replication of term B 0 for all counter terms of the binary counter.
39. The high speed binary counter according to claim 37 , wherein the means for redundant least significant terms includes replication of term B 0 for all counter terms of the binary counter.
40. A high speed binary counter, comprising:
a counting first flip-flop for each binary bit;
a single AND gate for each lower order binary bit beyond B 0 and B 1 ; and
a means for partial input factor delay for each higher order binary bit; and
further including means for redundant least significant terms for lesser order bits.