Thin film transistor and method for fabricating the same
View Patent ↗A thin film transistor formed by using a Metal Induced Lateral Crystallization process and method for fabricating the same. The thin film transistor comprises an active layer having source/drain regions and a channel region, a gate electrode, an insulating layer having contact holes for exposing a portion of each of the source/drain regions, and a crystallization inducing pattern exposing a portion of the active layer. The source/drain electrodes are coupled to the source/drain regions through the contact holes, and the crystallization inducing pattern does not couple the source/drain regions to the source/drain electrodes.
1. A thin film transistor (TFT), comprising:
an active layer having a source region, a drain region, and a channel region;
a gate electrode;
an insulating layer having a first contact hole exposing a portion of the source region, a second contact hole exposing a portion of the drain region, and a crystallization inducing pattern exposing a portion of the active layer; and
a source electrode coupled to the source region through the first contact hole, and a drain electrode coupled to the drain region through the second contact hole,
wherein the crystallization inducing pattern does not couple the source region to the source electrode or the drain region to the drain electrode.
2. The TFT of claim 1 , wherein the crystallization inducing pattern is formed between the channel region and a contact hole.
3. The TFT of claim 1 , wherein a width of the portion of the active layer exposed by the crystallization inducing pattern is larger than a width of a portion of the active layer exposed by a contact hole.
4. The TFT of claim 3 , wherein the width of the portion of the active layer exposed by the crystallization inducing pattern is the same as a width of the channel region.
5. A thin film transistor (TFT), comprising:
an active layer having a source region, a drain region, and a channel region;
a gate electrode;
an insulating layer having a first contact hole exposing a portion of the source region, a second contact hole exposing a portion of the drain region, and a crystallization inducing pattern exposing a portion of the active layer;
a source electrode coupled to the source region through the first contact hole, and a drain electrode coupled to the drain region through the second contact hole; and
a protection layer formed on the portion of the active layer exposed by the crystallization inducing pattern,
wherein the crystallization inducing pattern and the protection layer do not couple the source region to the source electrode or the drain region to the drain electrode.
6. The TFT of claim 5 , wherein the crystallization inducing pattern is formed between a contact hole and the channel region.
7. The TFT of claim 5 , wherein a width of the portion of the active layer exposed by the crystallization inducing pattern is larger than a width of a portion of the active layer exposed by a contact hole.
8. The TFT of claim 7 , wherein the width of the portion of the active layer exposed by the crystallization inducing pattern is the same as a width of the channel region.
9. The TFT of claim 7 , wherein the protection layer is a metal layer.
10. The TFT of claim 7 , wherein the protection layer is made of a same material as the source electrode and the drain electrode.
11. A method for fabricating a thin film transistor, comprising:
forming an active layer of amorphous silicon on an insulating substrate;
forming a gate electrode on a gate insulating layer;
forming a source region, a drain region, and a channel region in the active layer;
forming a first contact hole exposing a portion of the source region, a second contact hole exposing a portion of the drain region, and a crystallization inducing pattern exposing a portion of the active layer;
depositing a crystallization inducing layer on an entire surface of the insulating substrate;
crystallizing the active layer; and
forming a source electrode coupled the source region by the first contact hole, and a drain electrode coupled to the drain region by the second contact hole,
wherein the crystallization inducing pattern does not couple the source region to the source electrode or the drain region to the drain electrode.
12. The method of claim 11 , wherein the crystallization inducing layer has a thickness of 50 Å or more.
13. The method of claim 12 , wherein the crystallization inducing layer has a thickness of 200 Å or more.
14. The method of claim 11 ,
wherein the crystallization inducing layer is a metal layer; and
wherein the active layer is crystallized by a metal induced lateral crystallization process.
15. The method of claim 14 , wherein the metal layer is made of Ni.
16. The method of claim 11 , wherein the crystallization inducing pattern is formed between a contact hole and the channel region.
17. The method of claim 11 , wherein a width of the portion of the active layer exposed by the crystallization inducing pattern is larger than a width of a portion of the active layer exposed by a contact hole.
18. The method of claim 17 , wherein the width of the portion of the active layer exposed by the crystallization inducing pattern is the same as a width of the channel region.
19. The method of claim 11 , further comprising:
forming a protection layer on the portion of the active layer exposed by the crystallization inducing pattern,
wherein the protection layer does not couple the source region to the source electrode or the drain region to the drain electrode.
20. The method of claim 19 , wherein the protection layer is a passivation metal layer made of a same material as the source electrode and the drain electrode.