ESD protection for integrated circuits having ultra thin gate oxides
View Patent ↗According to an exemplary embodiment, an integrated circuit includes a first circuit block having a first power bus. The integrated circuit further includes a second circuit block having a second power bus, where the first power bus is isolated from the second power bus. The integrated circuit further includes a first dedicated ESD bus, where the first dedicated ESD bus provides a discharge path from the first power bus to the second power bus and from the second power bus to the first power bus. The first power bus can be coupled to the first dedicated ESD bus by a first pair to bi-directional diodes, and the second power bus can be coupled to the first dedicated ESD bus by a second pair of bi-directional diodes.
1. An integrated circuit comprising:
a first circuit block having a first power bus and a first inverter situated in said first circuit block;
a second circuit block having a second power bus and a second inverter situated in said second circuit block, said second inverter being coupled to said first inverter, said second power bus being isolated from said first power bus;
a digital block having a digital block power bus, said digital block being separated from said first circuit block and said second circuit block, said digital block being configured to transmit a signal from said first circuit block to said second circuit block;
wherein said first power bus and said second power bus are coupled to said digital block power bus.
2. The integrated circuit of claim 1 wherein said first power bus is coupled to said digital block power bus by a first pair of bi-directional diodes.
3. The integrated circuit of claim 2 wherein said second power bus is coupled to said digital block power bus by second pair of bi-directional diodes.
4. The integrated circuit of claim 1 wherein said digital block further comprises a third inverter coupled to a fourth inverter, wherein said third inverter and said fourth inverter are coupled to said digital block power bus, wherein an input of said third inverter is coupled to said first circuit block and an output of said fourth inverter is coupled to said second circuit block.
5. The integrated circuit of claim 4 wherein said first inverter is coupled to said first power bus, wherein an output of said first inverter is coupled to said input of said third inverter.
6. The integrated circuit of claim 4 wherein said second inverter is coupled to said second power bus, wherein an input of said second inverter is coupled to said output of said fourth inverter.