Method of fabricating an array substrate for IPS mode liquid crystal display device
View Patent ↗An array substrate for in-plane switching (IPS) mode liquid crystal display (LCD) device includes a gate line and a common line in a horizontal direction on a substrate, a data line crossing the gate line and the common line, a pixel electrode and a common electrode on the substrate, and a thin film transistor at a crossing point of the gate line and the data line, the thin film transistor having a gate electrode, an active layer and source and drain electrodes, the gate electrode having a slope that satisfies a numeral expression |θ R −θ g |=89°˜91° (degree) wherein θ R is an angle of a rubbing direction measured from an arbitrary horizontal line and θ g is an angle of the slope of the gate electrode measured from the arbitrary horizontal line.
1. A method of fabricating an array substrate for in-plane switching mode liquid crystal display device, comprising:
forming a gate line and a common line on a substrate;
forming a data line crossing the gate line and the common line;
forming a pixel electrode and a common electrode on the substrate;
forming a thin film transistor at a cross point of the gate line and the data line, the thin film transistor having a gate electrode, an active layer, a source electrode and a drain electrode; and
rubbing the substrate along a rubbing direction,
wherein the rubbing direction is parallel with an electric field direction between the gate electrode and the common electrode.
2. The method according to claim 1 , further comprising forming an alignment layer on the thin film transistor before the rubbing the substrate.
3. The method according to claim 1 , wherein the common electrode and the pixel electrode are formed in a zigzag pattern.
4. The method according to claim 1 , wherein the source and drain electrodes are formed over a portion of the gate line.
5. The method according to claim 1 , wherein the source electrode has an U-shape and the drain electrode is formed in an interior of the U-shape.
6. The method according to claim 1 , wherein the drain electrode has an I-shape.
7. The method according to claim 1 , wherein the rubbing direction is substantially perpendicular to the gate electrode.
8. The method according to claim 1 , wherein the pixel electrode has an extension portion, a plurality of vertical portions, and a horizontal portion.
9. The method according to claim 8 , wherein the extension portion of the pixel electrode is extended from the drain electrode.
10. The method according to claim 8 , wherein the vertical portions of the pixel electrode are vertically extended from the extended portion of the pixel electrode and are spaced apart from each other.
11. The method according to claim 8 , wherein the horizontal portion of the pixel electrode is disposed over the common line and connects the vertical portions of the pixel electrode into one portion.
12. The method according to claim 1 , wherein the common electrode has a plurality of vertical portions and a horizontal portion.
13. The method according to claim 12 , wherein the vertical portions of the common electrode are vertically extended from the common line and arranged in an alternative pattern with the vertical portions of the pixel electrode.
14. The method according to claim 12 , wherein the horizontal portion of the common electrode connects the vertical portions the common electrode into one portion.
15. The method according to claim 12 , wherein the horizontal portion of the common electrode has a side that is parallel with a slope of the gate electrode.
16. The method according to claim 1 , wherein the gate electrode has a slope that satisfies a numeral expression |θ R −θ g |=89°˜91° (degrees), wherein θ R is an angle of the rubbing direction and θ g is an angle of the slope of the gate electrode.
17. The method according to claim 16 , wherein the slope of the gate electrode is substantially perpendicular to the rubbing direction.