Array substrate for a liquid crystal display device and manufacturing method of the same
View Patent ↗An array substrate for a liquid crystal display device includes gate and data lines crossing on a substrate, common lines parallel to and between the gate lines, thin film transistors at crossing portions of the gate and data lines, and a pixel electrode. The common lines define pixel regions, which are each divided into first and second regions by the corresponding gate line. The thin film transistors each include a gate electrode in a first direction, a semiconductor layer on the gate electrode, and source and drain electrodes on the semiconductor layer in a second direction. The source and drain electrodes cross the gate electrode in each of the first and second regions. The pixel electrode is connected to the drain electrode.
1. A thin film transistor comprising:
a gate line extending in a first direction;
a gate electrode formed along a portion of the gate line and defined by an expanded area having a width greater than a width of the gate line;
a semiconductor layer on the gate electrode; and
source and drain electrodes on the semiconductor layer, the drain electrode crossing the entire the expanded area of the gate electrode and having a first portion extending past the expanded area in a second direction, and a second portion extending past the expanded area in a third opposite direction such that an area of overlap between the drain electrode and the expanded area remains constant for a predetermined change in placement of the drain electrode relative to the gate electrode wherein the source and drain electrodes extend in the same direction.
2. The thin film transistor according to claim 1 , wherein the gate electrode has a rectangle shape, and the source and drain electrodes have rod-like shapes.
3. The thin film transistor according to claim 1 , wherein the drain electrode extends in a direction substantially orthogonal to the first direction.
4. The thin film transistor according to claim 1 , wherein the drain electrode extends in multiple directions.
5. The thin film transistor according to claim 1 , wherein the source electrode crosses the entire expanded area of the gate electrode and includes a first portion extending past the expanded area in a first direction, and a second portion extending past the expanded area in a second opposite direction such that an area of overlap between the source electrode and the expanded area remains constant for a predetermined change in placement of the source electrode relative to the gate electrode.
6. The thin film transistor according to claim 1 , wherein the drain electrode is substantially longer than the gate electrode.
7. The thin film transistor according to claim 6 , wherein a length of a portion of the drain electrode that overlaps the expanded area of the gate electrode is at most twice a length of the first and second portions of the drain electrode that do not overlap the expanded area of the gate electrode.
8. The thin film transistor according to claim 1 , wherein the drain electrode is substantially symmetric around the gate electrode.
9. An array substrate for a liquid crystal display device, the array substrate comprising:
a gate line;
common lines parallel to the gate line, the gate line disposed between the common lines;
a data line crossing the gate line and the common lines to define a pixel region, the pixel region divided into first and second regions by the gate line;
a thin film transistor at a crossing portion of the gate and data lines, the thin film transistor comprising:
a gate electrode formed along a portion of the gate line and defined by an expanded area having a width greater than a width of the gate line;
a semiconductor layer on the gate electrode;
source and drain electrodes on the semiconductor layer, the drain electrode crossing the entire expanded area of the gate electrode and having a first portion extending past the expanded area in a first direction, and a second portion extending past the expanded area in a second opposite direction such that an area of overlap between the drain electrode and the expanded area remains constant for a predetermined change in placement of the drain electrode relative to the gate electrode;
the drain electrode crossing the entire gate electrode along a second direction perpendicular to the first direction; and
a pixel electrode in each of the first and second regions, the pixel electrodes connected to the drain electrode wherein the source and drain electrodes extend in the same direction.
10. The array substrate according to claim 9 , wherein the drain electrode extends parallel to the data line.
11. The array substrate according to claim 9 , wherein the drain electrode extends in a direction substantially orthogonal to the first direction.
12. The array substrate according to claim 9 , wherein the drain electrode extends in multiple directions.
13. The array substrate according to claim 9 , wherein the source electrode crosses the entire expanded area of the gate electrode and includes a first portion extending past the expanded area in a first direction, and a second portion extending past the expanded area in a second opposite direction such that an area of overlap between the source electrode and the expanded area remains constant for a predetermined change in placement of the source electrode relative to the gate electrode.
14. The array substrate according to claim 9 , wherein a length of a portion of the drain electrode that overlaps the expanded area of the gate electrode is at most twice a length of the first and second portions of the drain electrode that do not overlap the expanded area of the gate electrode.
15. The array substrate according to claim 9 , wherein the drain electrode is symmetric around the gate electrode.
16. A method of manufacturing an array substrate for a liquid crystal display device, the method comprising:
forming a gate line on a substrate;
forming common lines parallel to the gate line, the gate line disposed between the common lines;
forming a data line crossing the gate line and the common lines to define a pixel region, the pixel region divided into first and second regions by the gate line;
forming a thin film transistor at a crossing portion of the gate and data lines, the thin film transistor comprising:
a gate electrode formed along a portion of the gate line and defined by an expanded area having a width greater than a width of the gate line;
a semiconductor layer on the gate electrode;
source and drain electrodes on the semiconductor layer, the drain electrode crossing the entire expanded area of the gate electrode and having a first portion extending past the expanded area in a first direction, and a second portion extending past the expanded area in a second opposite direction such that an area of overlap between the drain electrode and the expanded area remains constant for a predetermined change in placement of the drain electrode relative to the gate electrode;
the drain electrode crossing the entire gate electrode along a second direction perpendicular to the first direction; and
forming a pixel electrode in each of the first and second regions, each pixel electrode connected to the drain electrode wherein the source and drain electrodes extend in the same direction.
17. The method according to claim 16 , wherein the common line is formed simultaneously with the gate line.