Thin film transistor using a metal induced crystallization process and method for fabricating the same and active matrix flat panel display using the thin film transistor
View Patent ↗Provided is a thin film transistor that may be manufactured using Metal Induced Crystallization (MIC) and method for fabricating the same. Also provided is an active matrix flat panel display using the thin film transistor, which may be created by forming a crystallization inducing metal layer below a buffer layer and diffusing the crystallization inducing metal layer. The thin film transistor may include a crystallization inducing metal layer formed on an insulating substrate, a buffer layer formed on the crystallization inducing metal layer, and an active layer formed on the buffer layer and including source/drain regions, and including polycrystalline silicon crystallized by the MIC process.
1. A thin film transistor, comprising:
a crystalline inducing metal layer formed on a substrate;
a buffer layer formed on the crystalline inducing metal layer; and
an active layer formed on the buffer layer and including source/drain regions, and comprising polycrystalline silicon crystallized by metal induced crystallization (MIC), said active layer containing an amount of metallic material ranging from about 1E+11/cm 2 to about 1E+12/cm 2 coming from said crystalline inducing metal layer.
2. The thin film transistor of claim 1 , wherein the crystalline inducing metal layer is formed of at least any one metallic material selected from a group of Ni, Al, Pt, Pd, Pb, Co, and an alloy thereof.
3. The thin film transistor of claim 1 , wherein the buffer layer acts as a diffusion path for the crystalline inducing metal layer.
4. A flat panel display, comprising:
a crystalline inducing metal layer formed on a substrate;
a buffer layer formed on the crystalline inducing metal layer;
an active layer formed on the buffer layer and including source/drain regions, and comprising polycrystalline silicon crystallized by metal induced crystallization (MIC), said active layer containing an amount of metallic material ranging from about 1E+11/cm 2 to about 1E+12/cm 2 coming from said crystalline inducing metal layer;
a gate insulating layer formed on the active layer;
a gate electrode formed on the gate insulating layer;
an interlayer insulating layer formed on the gate electrode;
source/drain electrodes electrically connected to the source/drain regions through contact holes of the interlayer insulating layer; and
a light emitting diode electrically connected to at least any one of the source/drain electrodes.
5. The flat panel display of claim 4 , wherein the substrate includes an emission region and a TFT region, and the crystalline inducing metal layer is formed only in the TFT region.
6. The flat panel display of claim 5 , wherein the crystalline inducing metal layer formed only in the TFT region acts as a light blocking layer for blocking external light.
7. The flat panel display of claim 4 , wherein the crystalline inducing metal layer is formed of at least any one metallic material selected from a group of Ni, Al, Pt, Pd, Pb, Co, and an alloy thereof.
8. The flat panel display of claim 4 , wherein the buffer layer acts as a diffusion path for the crystalline inducing metal layer.
9. The flat panel display of claim 4 , wherein the flat panel display is any one of a liquid crystal display and an organic light emitting display.