Semiconductor device fabrication method
View Patent ↗A semiconductor device fabrication method comprises; a first step S 1 of fabricating a plurality of semiconductor chips on a plurality of semiconductor wafers, respectively; a second step S 4 of making a probe test on the plural semiconductor chips respectively, which are present in a sampling region of one semiconductor wafer of the plural semiconductor wafers; and the third step S 5 of computing a yield of the plural semiconductor chips present in the sampling region, when the yields of the plural semiconductor chips computed in the third step are a reference value or above, the probe test is not made on the plural semiconductor chips, which are present outside the sampling region of said one semiconductor wafer and on the rest semiconductor wafers of the plural semiconductor wafers fabricated in the same lot as said one semiconductor wafer. The probe test is made on the plural semiconductor chips respectively, which are present in the sampling region of said one semiconductor wafer of the plural semiconductor wafers, and when the yield of the semiconductor chips present in the sampling region is the reference value or above, the probe test is not made on the rest semiconductor chips present in the rest region of said one semiconductor wafer other than the sampling region and on the rest semiconductor wafers fabricated in the same lot as said one semiconductor wafer, whereby the inspection period of time can be drastically shortened.
1. A semiconductor device fabrication method comprising;
a first step of fabricating a plurality of semiconductor chips on a plurality of semiconductor wafers, respectively;
a second step of making a probe test on said plurality of semiconductor chips respectively, which are present in a sampling region of one semiconductor wafer of said plurality of semiconductor wafers; and
a third step of computing a yield of said plurality of semiconductor chips present in the sampling region,
when the yield of said plurality of semiconductor chips computed in the third step are a reference value or above, the probe test being not made on said plurality of semiconductor chips, which are present outside the sampling region of said one semiconductor wafer and on the rest semiconductor wafers of said plurality of semiconductor wafers fabricated in the same lot as said one semiconductor wafer.
2. A semiconductor device fabrication method according to claim 1 , wherein
when an average value of a plurality of yields of a plurality of semiconductor chips in sampling regions of a plurality of semiconductor wafers is m, and a standard deviation of said plurality of yields of said plurality of semiconductor chips in the sampling regions of said plurality of semiconductor wafers is σ, a value of m−2σ is the reference value when the value of m−2σ is a first value or above, and when the value of m−2σ is below the first value, the first value is the reference value.
3. A semiconductor device fabrication method according to claim 1 , further comprising, after the first step and before the second step,
a fourth step of detecting numbers of particles adhering to a surface of the said plurality of semiconductor wafers,
when the number of particles adhering to the surface of the semiconductor wafer is a second value or above, the probe test is made on all the semiconductor chips fabricated on said semiconductor wafer.
4. A semiconductor device fabrication method according to claim 1 , wherein
the first step includes the step of using a reticle having patterns of said plurality of semiconductor chips to sequentially expose the patterns, and
the sampling region contains a first partial region where the pattern of the semiconductor chip, which is positioned at an edge of the reticle, is exposed.
5. A semiconductor device fabrication method according to claim 2 , wherein
the first step includes the step of using a reticle having patterns of said plurality of semiconductor chips to sequentially expose the patterns, and
the sampling region contains a first partial region where the pattern of the semiconductor chip, which is positioned at an edge of the reticle, is exposed.
6. A semiconductor device fabrication method according to claim 3 , wherein
the first step includes the step of using a reticle having patterns of said plurality of semiconductor chips to sequentially expose the patterns, and
the sampling region contains a first partial region where the pattern of the semiconductor chip, which is positioned at an edge of the reticle, is exposed.
7. A semiconductor device fabrication method according to claim 4 , wherein
the first partial region is an L-shaped region which is positioned between a central part of said one semiconductor wafer and a peripheral part thereof.
8. A semiconductor device fabrication method according to claim 5 , wherein
the first partial region is an L-shaped region which is positioned between a central part of said one semiconductor wafer and a peripheral part thereof.
9. A semiconductor device fabrication method according to claim 6 , wherein
the first partial region is an L-shaped region which is positioned between a central part of said one semiconductor wafer and a peripheral part thereof.
10. A semiconductor device fabrication method according to claim 4 , wherein
the sampling region contains a second partial region which is positioned at a central part of said one semiconductor wafer.
11. A semiconductor device fabrication method according to claim 5 , wherein
the sampling region contains a second partial region which is positioned at a central part of said one semiconductor wafer.
12. A semiconductor device fabrication method according to claim 6 , wherein
the sampling region contains a second partial region which is positioned at a central part of said one semiconductor wafer.
13. A semiconductor device fabrication method according to claim 7 , wherein
the sampling region contains a second partial region which is positioned at a central part of said one semiconductor wafer.
14. A semiconductor device fabrication method according to claim 8 , wherein
the sampling region contains a second partial region which is positioned at a central part of said one semiconductor wafer.
15. A semiconductor device fabrication method according to claim 9 , wherein
the sampling region contains a second partial region which is positioned at a central part of said one semiconductor wafer.
16. A semiconductor device fabrication method according to claim 4 , wherein
the sampling region contains a third partial region which is positioned at a peripheral part of said one semiconductor wafer.
17. A semiconductor device fabrication method according to claim 5 , wherein
the sampling region contains a third partial region which is positioned at a peripheral part of said one semiconductor wafer.
18. A semiconductor device fabrication method according to claim 6 , wherein
the sampling region contains a third partial region which is positioned at a peripheral part of said one semiconductor wafer.
19. A semiconductor device fabrication method according to claim 7 , wherein
the sampling region contains a third partial region which is positioned at the peripheral part of said one semiconductor wafer.
20. A semiconductor device fabrication method according to claim 8 , wherein
the sampling region contains a third partial region which is positioned at the peripheral part of said one semiconductor wafer.