IP Library Granted Patent US 7,288,444
Granted Patent B2
US 7,288,444 · App. 10/994,265 · Granted Oct 30, 2007

Thin film transistor and method of manufacturing the same

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Quick Facts
Patent No.
US 7,288,444
App. No.
10/994,265
Granted
Oct 30, 2007
Kind
B2
Abstract

A method of manufacturing a thin film transistor that provides high electric field mobility is disclosed. In one embodiment, the method includes: a) forming an amorphous silicon layer and a blocking layer on an insulating substrate; b) forming a photoresist layer having first and second photoresist patterns on the blocking layer, the first and second photoresist patterns spaced apart from each other; c) etching the blocking layer using the first photoresist pattern as a mask to form first and second blocking patterns; d) reflowing the photoresist layer, so that the first and second photoresist patterns abut on each other to entirely cover the first and second blocking patterns; e) forming a capping layer and a metal layer over an entire first surface of the insulating substrate; f) removing the photoresist layer to expose the blocking layer and an offset region between the blocking layer and the metal layer; g) crystallizing the amorphous silicon layer by diffusing metals in the metal layer through the capping into the amorphous silicon layer; h) etching the poly silicon layer using the first and second blocking patterns as a mask to form first and second semiconductor layers; and i) removing the first and second blocking patterns.

Claims (33)

1. A method of manufacturing a thin film transistor, comprising:

a) forming an amorphous silicon layer and a blocking layer on an insulating substrate;

b) forming a photoresist layer having first and second photoresist patterns on the blocking layer, the first and second photoresist patterns spaced apart from each other;

c) etching the blocking layer using the first photoresist pattern as a mask to form first and second blocking patterns;

d) reflowing the photoresist layer, so that the first and second photoresist patterns abut on each other to entirely cover the first and second blocking patterns;

e) forming a capping layer and a metal layer over an entire first surface of the insulating substrate;

f) removing the photoresist layer to expose the blocking layer and an offset region between the blocking layer and the metal layer;

g) crystallizing the amorphous silicon layer by diffusing metals in the metal layer through the capping layer into the amorphous silicon layer to form a polysilicon layer;

h) etching the poly silicon layer using the first and second blocking patterns as a mask to form first and second semiconductor layers; and

i) removing the first and second blocking patterns.

2. The method of claim 1 , wherein the metal layer is made of Ni or Pd and has a thickness of 1 Å to 5000 Å.

3. The method of claim 1 , wherein the capping layer is made of SiO2 or SiNx.

4. The method of claim 1 , further comprising, after the step (i), surface-treating the first and second semiconductor layers.

5. The method of claim 4 , wherein the surface treatment is performed using a dry-etching technique or an HF etching solution of 0.1% to 20%.

6. The method of claim 1 , wherein the blocking layer is patterned using a dry-etching technique or an HF etching solution of 0.1% to 20%.

7. The method of claim 1 , further comprising, before the step (a), forming a buffer layer on the insulating substrate.

8. The method of claim 1 , wherein a high angle grain boundary formed in the step (g) is removed by etching process in the step (h).

9. The method of claim 1 , further comprising:

j) forming a gate insulating layer over said entire first surface of the insulating substrate;

k) forming a gate electrode on the gate insulating layer over the first and second semiconductor layers;

l) forming an interlayer insulating layer over said entire first surface of the insulating substrate;

m) etching the interlayer insulating layer to form contact holes; and

n) forming a source and drain electrode.

10. The method of claim 9 , wherein the first and second semiconductor layers electrically coupled by the same layer as the gate electrode with each other.

11. The method of claim 9 , wherein the first and second semiconductor layers electrically coupled by the same layer as the source and drain electrode with each other.

12. The method of claim 9 , wherein the gate insulating layer over the first and second semiconductor layers has at least two contact holes in each other.

13. A thin film transistor manufactured by the method of claim 1 .

14. The method of claim 1 , wherein the first and second semiconductor layers electrically coupled by the same layer as the gate electrode with each other.

15. The method of claim 1 , wherein the first and second semiconductor layers electrically coupled by the same layer as the source and drain electrode with each other.

16. The method of claim 1 , wherein the gate insulating layer over the first and second semiconductor layers has at least two contact holes in each other.

17. A thin film transistor manufactured by the method of claim 1 .

18. The method of claim 1 , wherein in the step (g), a portion of the amorphous layer directly contacting the capping layer includes seeds, and the remaining portion of the amorphous silicon layer is crystallized through the SGS, so that a high-angle grain boundary exists on a portion of the poly silicon layer between the first and second blocking patterns.

19. The method of claim 1 , further comprising: removing the capping and the metal layer.

Assignments (3)
MERGER Recorded Aug 29, 2012
From: SAMSUNG MOBILE DISPLAY CO., LTD.
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 028868/0326 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2008
From: SAMSUNG SDI CO., LTD.
To: SAMSUNG MOBILE DISPLAY CO., LTD.
Reel/Frame 022024/0026 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 23, 2004
From: SO, WOO-YOUNG
To: SAMSUNG SDI CO., LTD.
Reel/Frame 016028/0400 →